Patents by Inventor Arch Robison

Arch Robison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8127303
    Abstract: Implementing fair scalable reader writer mutual exclusion for access to a critical section by a plurality of processing threads in a processing system is accomplished by creating a first queue node for a first thread on the first thread's stack, the queue node representing a request by the first thread to access the critical section; adding the first queue node to a queue pointed to by a single word reader writer mutex for the critical section, the queue representing a list of threads desiring access to the critical section, each queue node in the queue being on a stack of a thread of the plurality of processing threads; waiting until the first queue node has no preceding write requests as indicated by predecessor queue nodes on the queue; entering the critical section by the first thread; exiting the critical section by the first thread; and removing the first queue node from the queue.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: February 28, 2012
    Assignee: Intel Corporation
    Inventors: Alexey Kukanov, Arch Robison
  • Publication number: 20100293553
    Abstract: Implementing fair scalable reader writer mutual exclusion for access to a critical section by a plurality of processing threads in a processing system is accomplished by creating a first queue node for a first thread on the first thread's stack, the queue node representing a request by the first thread to access the critical section; adding the first queue node to a queue pointed to by a single word reader writer mutex for the critical section, the queue representing a list of threads desiring access to the critical section, each queue node in the queue being on a stack of a thread of the plurality of processing threads; waiting until the first queue node has no preceding write requests as indicated by predecessor queue nodes on the queue; entering the critical section by the first thread; exiting the critical section by the first thread; and removing the first queue node from the queue.
    Type: Application
    Filed: May 18, 2010
    Publication date: November 18, 2010
    Inventors: Alexey Kukanov, Arch Robison
  • Patent number: 7730491
    Abstract: Implementing fair scalable reader writer mutual exclusion for access to a critical section by a plurality of processing threads in a processing system is accomplished by creating a first queue node for a first thread on the first thread's stack, the queue node representing a request by the first thread to access the critical section; adding the first queue node to a queue pointed to by a single word reader writer mutex for the critical section, the queue representing a list of threads desiring access to the critical section, each queue node in the queue being on a stack of a thread of the plurality of processing threads; waiting until the first queue node has no preceding write requests as indicated by predecessor queue nodes on the queue; entering the critical section by the first thread; exiting the critical section by the first thread; and removing the first queue node from the queue.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: June 1, 2010
    Assignee: Intel Corporation
    Inventors: Alexey Kukanov, Arch Robison
  • Patent number: 7213242
    Abstract: An arrangement is provided for eliminating partial redundancy. Original code is processed to perform run-time behavior preserving redundancy elimination. Partial redundancy is removed in a manner so that the run-time behavior of the original code is preserved.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: May 1, 2007
    Assignee: Intel Corporation
    Inventor: Arch Robison
  • Publication number: 20070094652
    Abstract: A loop can be executed on a parallel processor by partitioning the loop iterations into chunks of decreasing size. An increase in speed can be realized by reducing the time taken by a thread when determining the next set of iterations to be assigned to a thread. The next set of iterations can be determined from a chunk index stored in a shared variable. Using a shared variable enables threads to perform operations concurrently to reduce the wait time to the period while another thread increments the shared variable.
    Type: Application
    Filed: October 21, 2005
    Publication date: April 26, 2007
    Inventors: Joshua Chia, Arch Robison, Grant Haab
  • Publication number: 20070067774
    Abstract: Implementing fair scalable reader writer mutual exclusion for access to a critical section by a plurality of processing threads in a processing system is accomplished by creating a first queue node for a first thread on the first thread's stack, the queue node representing a request by the first thread to access the critical section; adding the first queue node to a queue pointed to by a single word reader writer mutex for the critical section, the queue representing a list of threads desiring access to the critical section, each queue node in the queue being on a stack of a thread of the plurality of processing threads; waiting until the first queue node has no preceding write requests as indicated by predecessor queue nodes on the queue; entering the critical section by the first thread; exiting the critical section by the first thread; and removing the first queue node from the queue.
    Type: Application
    Filed: August 30, 2005
    Publication date: March 22, 2007
    Inventors: Alexey Kukanov, Arch Robison
  • Publication number: 20060136468
    Abstract: A dependence graph having a linear number of edges and one or more tie vertices is generated by constructing a tree of nodes, receiving requests to create cut and/or fan vertices corresponding to each node, adjusting a frontier of nodes up or down, and creating one or more cut or fan vertices, zero or more tie vertices, and at least one predecessor edge.
    Type: Application
    Filed: December 16, 2004
    Publication date: June 22, 2006
    Inventor: Arch Robison
  • Patent number: 7062759
    Abstract: Interprocedural side-effect analysis is performed by constructing a fixed-point problem graph for each translation unit of a software program having a plurality of separately compilable components. The method performs analyzing each routine, of a software program having a plurality of separately compilable routines, to create a plurality of local side-effect problems for each routine; and merging the local side-effect problems to create a global side-effect problem.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: June 13, 2006
    Assignee: Intel Corporation
    Inventor: Arch Robison
  • Publication number: 20050289209
    Abstract: An integer division system for a dividend and a divisor includes a pre-calculation module to select a reciprocal approximation and a rounding error compensation value of the divisor, and an instruction generation module to generate at least an instruction to calculate a quotient of the dividend using the reciprocal and the rounding error compensation value. The reciprocal approximation is of the same predetermined number of binary bits as the divisor and the pre-calculation module determines which one of rounding-up and rounding-down is used when selecting the reciprocal approximation and the rounding error compensation value.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 29, 2005
    Inventor: Arch Robison
  • Publication number: 20050289530
    Abstract: A method and apparatus for scheduling of instructions for program compilation are provided. An embodiment of a method comprises placing a plurality of computer instructions in a plurality of priority queues, each priority queue representing a class of computer instruction; maintaining a state value, the state value representing any computer instructions that have previously been placed in a instruction group; and identifying one or more computer instructions as candidates for placing in the instruction group based at least in part on the state value.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 29, 2005
    Inventor: Arch Robison
  • Publication number: 20040015903
    Abstract: A method and system for interprocedural side-effect analysis is disclosed. In one embodiment, the method is applied to a software program having a plurality of separately compilable components. The method performs analyzing each routine, of a software program having a plurality of separately compilable routines, to create a plurality of local side-effect problems for each routine; and merging the local side-effect problems to create a global side-effect problem.
    Type: Application
    Filed: April 19, 2001
    Publication date: January 22, 2004
    Inventor: Arch Robison