Abstract: A tissue ablation system employing a radiofrequency generator and a radiofrequency probe, where a generator controller can be employed to automate selected operational modes of the generator. The operational modes can include determining if the probe is connected to the generator, determining the location of the probe, and determining an impedance of the probe. The generator can also display multiple channels on a display element, and the controller can generate summary information of the ablation procedure, including information associated with probe impedance and temperature and the power supplied by the generator.

Abstract: In some embodiments, a method includes positioning a semiconductor structure within a processing chamber. The semiconductor structure includes a first layer disposed over a substrate surface. The semiconductor structure further includes a second layer disposed over the first layer. The second layer has a hardmask layer. The semiconductor structure further includes one or more second dielectric layers disposed over the second layer. The one or more second dielectric layers have a gap formed over a portion of the second layer. The semiconductor structure further includes a metal material disposed within the gap formed over the second layer. The metal material has a molybdenum oxide (MoOx) layer. The method further includes flowing a process gas into the processing chamber, and performing a redox operation on a portion of the semiconductor structure to reduce the MoOx to molybdenum (Mo). The redox operation includes applying a microwave energy to the process gas.

Abstract: A method of substrate topography correction. The method may include receiving a thickness map of a substrate, the thickness map defining a total thickness variation across the substrate, and providing a greyscale photoresist layer on a first surface of the substrate. The method may further include performing a greyscale lithography operation on the greyscale photoresist layer, based upon the thickness map, wherein the greyscale lithography operation is to reduce the total thickness variation.

Abstract: A method for bonding wafers is provided. More specifically, the method provides for forming a hybrid bond between wafers that compensates for warpage and offset on each of the wafers being bonded.

Abstract: The present subject matter relates to systems and methods for producing a MOSFET by applying a nitridation pre-treatment (e.g., plasma or thermal) directly on a silicon carbide surface. The nitridation pre-treatment can be followed by a deposited gate oxide. In this way, instead of using a thermal oxide and a thermal nitrogen oxide anneal, nitrogen is introduced at the interface to passivate traps without any thermal oxidation of the silicon carbide. In addition, the post-anneal step can be performed, resulting in an improvement in mobility.

Abstract: Methods and substrate processing systems of chucking a bowed substrate are provided herein. In some embodiments, a substrate processing system includes: a pedestal to support a substrate, the pedestal having a plurality of chucking regions; a warpage detection system having one or more sensors to detect warpage of the substrate; and a plurality of adjustable chucking components disposed in the pedestal corresponding with the plurality of chucking regions, wherein the plurality of adjustable chucking components are configured to facilitate applying different amounts of force, heating, or cooling to the substrate based on the warpage of the substrate.

Abstract: A method for processing a substrate for hybrid bonding that includes doping an aluminum oxide (Al2O3) layer prior to bonding of the substrate. A method may include forming an aluminum oxide layer with a metal dopant to form a doped aluminum oxide layer on the substrate where the doped aluminum oxide forms a bonding layer for a hybrid bonding process on an uppermost surface of the substrate. A metal contact is formed on the substrate that penetrates through the doped aluminum oxide layer and a chemical mechanical polish (CMP) process is performed to recess an uppermost surface of the metal contact below a surface of the doped aluminum oxide layer.

Abstract: A method for substrate processing for hybrid bonding that includes forming an aluminum oxide crystallization barrier on a metal contact. In some embodiments, the method may include providing a substrate in preparation for a hybrid bonding process where the substrate has an aluminum oxide (Al2O3) bonding layer on an uppermost surface of the substrate and a metal contact is present in the aluminum oxide bonding layer. A crystallization barrier is formed on an uppermost surface of the metal contact. The crystallization barrier disrupts crystallization of the aluminum oxide bonding layer caused by interaction of the aluminum oxide material of the aluminum oxide bonding layer and a metal material of the metal contact during a subsequent annealing process of the hybrid bonding process.

Abstract: A method for preparing a substrate for hybrid bonding by forming an isolation barrier around metal contacts on the substrate to separate the metal contacts from an aluminum oxide (Al2O3) bonding layer prior to performing the hybrid bonding process. A method may include forming an aluminum oxide layer on the substrate as a bonding layer for a hybrid bonding process where the aluminum oxide layer is formed on a dielectric material on the substrate that is different from a material of the aluminum oxide layer, forming a metal contact on the substrate that penetrates through the aluminum oxide layer, and forming an isolation barrier around the metal contact where the isolation barrier prevents adjacent portions of the aluminum oxide layer next to the metal contact from completely covering an uppermost bonding surface of the metal contact during an annealing process of the hybrid bonding process.

Abstract: The methods of the present disclosure enable formation of highly conductive contacts that facilitate in increasing the device speed and lowering the operating voltages of semiconductor devices such as, but not limited to, metal-on-semiconductor (MOS) transistors and the like. In one embodiment, the methods create the optimal contacts, useful in N type or P type MOS devices, by forming metal-insulator-semiconductor (MIS) contact structure or a non-stoichiometric layer contact structure. It is noted that N type or P type contacts require different work function metals to achieve a low Schottky barrier height (SBH).

Abstract: Exemplary semiconductor processing methods may include performing a treatment operation on a substrate housed within a first processing region of a first semiconductor processing chamber. The methods may include providing a nitrogen-containing precursor to the first processing region. The methods may include forming plasma effluents of the nitrogen-containing precursor. The methods may include contacting the substrate with the plasma effluents of the nitrogen-containing precursor. The contacting may nitride a surface of the substrate. The methods may include transferring the substrate from the first processing region of the first semiconductor processing chamber to a second processing region of a second semiconductor processing chamber. The methods may include providing one or more deposition precursors to the second processing region. The methods may include contacting the substrate with the one or more deposition precursors. The contacting may deposit a layer of dielectric material on the substrate.

Abstract: Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.

Abstract: A mesa etch may form the geometry of microLED structures. However, the mesa etch may induce defects in the microLED structures that decreases the efficiency of the microLEDs. To correct these defects, a dry etch process may be performed that incrementally removes the surface layers of the microLED structures with the defects. The dry etch may be configured to incrementally remove a small outer layer, and thus may preserve the overall shape of the microLED structures while leaving a smooth surface for the application of a dielectric layer. The dry etch process may include two steps that are repeatedly performed. A first gas may react with the surface to form a gallium compound layer, and a second gas may then selectively remove that layer. The dry etch may include plasma-based etches or reactive thermal etches.

Abstract: A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.

Abstract: Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.

Abstract: Method of forming film stacks and film stacks for electronic devices are described herein. The methods comprise depositing a molybdenum nucleation layer on a gate oxide layer; depositing a molybdenum layer on the molybdenum nucleation layer; and performing a plasma nitridation process to insert nitrogen atoms into the molybdenum layer to form a work function modulating layer having an effective work function ? 4.5 eV. The plasma nitridation process comprises exposing the molybdenum layer to a radical-rich plasma comprising one or more of N2 or NH3. Some methods further comprise one or more of annealing the work function modulating layer, depositing a conductive layer on the work function modulating layer, or performing an etch process.

Abstract: Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.

Abstract: Exemplary methods of forming a semiconductor structure may include forming a layer of metal on a semiconductor substrate. The layer of metal may extend along a first surface of the semiconductor substrate. The semiconductor substrate may be or include silicon. The methods may include performing an anneal to produce a metal silicide. The methods may include implanting ions in the metal silicide to increase a barrier height over 0.65 V.

Abstract: Embodiments of the present disclosure provide methods of forming solid state dual pore sensors which may be used for biopolymer sequencing and dual pore sensors formed therefrom. In one embodiment, a method of forming a dual pore sensor includes providing a pattern in a surface of a substrate. Generally, the pattern features two fluid reservoirs separated by a divider wall. The method further includes depositing a layer of sacrificial material into the two fluid reservoirs, depositing a membrane layer, patterning two nanopores through the membrane layer, removing the sacrificial material from the two fluid reservoirs, and patterning one or more fluid ports and a common chamber.

Abstract: Embodiments of the present disclosure provide methods of forming solid state dual pore sensors which may be used for biopolymer sequencing and dual pore sensors formed therefrom. In one embodiment, a dual pore sensor features a substrate having a patterned surface comprising two recessed regions spaced apart by a divider wall and a membrane layer disposed on the patterned surface. The membrane layer, the divider wall, and one or more surfaces of each of the two recessed regions collectively define a first fluid reservoir and a second fluid reservoir. A first nanopore is disposed through a portion of the membrane layer disposed over the first fluid reservoir and a second nanopore is disposed through a portion of the membrane layer disposed over the second fluid reservoir. Herein, opposing surfaces of the divider wall are sloped to each form an angle of less than 90° with a respective reservoir facing surface of the membrane layer.