Patents by Inventor Archana SRINIVASAIAH

Archana SRINIVASAIAH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock gating coupled memory retention circuit
    Patent number: 11003238
    Abstract: A hierarchy of interconnected memory retention (MR) circuits detect a clock gating mode being entered at any level of an integrated circuit. In response, the hierarchy automatically transitions memory at the clock gated level and all levels below the clock-gated level from a normal operating state to a memory retention state. When a memory transitions from a normal operating state to a memory retention state, the memory transitions from a higher power state (corresponding to the normal operating state) to a lower power state (corresponding to the memory retention state). Thus, in addition to the dynamic power savings caused by the clock gating mode, the hierarchy of MR circuits automatically transitions the memory modules at the clock gated level and all levels below the clock gated level to a lower power state. As a result, the leakage power consumption of the corresponding memory modules is reduced relative to prior approaches.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: May 11, 2021
    Assignee: NVIDIA Corporation
    Inventors: Anand Shanmugam Sundararajan, Ramachandiran V, Abhijeet Chandratre, Lordson Yue, Archana Srinivasaiah, Sachin Idgunji
  • CLOCK GATING COUPLED MEMORY RETENTION CIRCUIT
    Publication number: 20180284874
    Abstract: A hierarchy of interconnected memory retention (MR) circuits detect a clock gating mode being entered at any level of an integrated circuit. In response, the hierarchy automatically transitions memory at the clock gated level and all levels below the clock-gated level from a normal operating state to a memory retention state. When a memory transitions from a normal operating state to a memory retention state, the memory transitions from a higher power state (corresponding to the normal operating state) to a lower power state (corresponding to the memory retention state). Thus, in addition to the dynamic power savings caused by the clock gating mode, the hierarchy of MR circuits automatically transitions the memory modules at the clock gated level and all levels below the clock gated level to a lower power state. As a result, the leakage power consumption of the corresponding memory modules is reduced relative to prior approaches.
    Type: Application
    Filed: May 1, 2017
    Publication date: October 4, 2018
    Inventors: Anand Shanmugam SUNDARARAJAN, Ramachandiran V, Abhijeet CHANDRATRE, Lordson YUE, Archana SRINIVASAIAH, Sachin IDGUNJI