Patents by Inventor Archana Srinivasan

Archana Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High bandwidth link layer for coherent messages
    Patent number: 11366773
    Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: June 21, 2022
    Assignee: Intel Corporation
    Inventors: Ishwar Agarwal, Peeyush Purohit, Nitish Paliwal, Archana Srinivasan
  • HIGH BANDWIDTH LINK LAYER FOR COHERENT MESSAGES
    Publication number: 20200334179
    Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.
    Type: Application
    Filed: April 3, 2020
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Ishwar Agarwal, Peeyush Purohit, Nitish Paliwal, Archana Srinivasan
  • High bandwidth link layer for coherent messages
    Patent number: 10614000
    Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Ishwar Agarwal, Peeyush Purohit, Nitish Paliwal, Archana Srinivasan
  • HIGH BANDWIDTH LINK LAYER FOR COHERENT MESSAGES
    Publication number: 20190095363
    Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 28, 2019
    Applicant: Intel Corporation
    Inventors: Ishwar Agarwal, Peeyush Purohit, Nitish Paliwal, Archana Srinivasan