Patents by Inventor Ardechir Pakfar
Ardechir Pakfar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9972721Abstract: A method of forming a semiconductor device is disclosed including providing a semiconductor-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulating layer positioned on the semiconductor bulk substrate and a semiconductor layer positioned on the buried insulating layer, providing at least one metal-oxide semiconductor gate structure positioned above the semiconductor layer comprising a gate electrode and a spacer formed adjacent to the gate electrode, selectively removing an upper portion of the semiconductor layer so as to define recessed portions of the semiconductor layer and epitaxially forming raised source/drain regions on the recessed portions of the semiconductor layer.Type: GrantFiled: October 28, 2016Date of Patent: May 15, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Marcel Richter, Ardechir Pakfar, Armin Muehlhoff
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Publication number: 20180122956Abstract: A method of forming a semiconductor device is disclosed including providing a semiconductor-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulating layer positioned on the semiconductor bulk substrate and a semiconductor layer positioned on the buried insulating layer, providing at least one metal-oxide semiconductor gate structure positioned above the semiconductor layer comprising a gate electrode and a spacer formed adjacent to the gate electrode, selectively removing an upper portion of the semiconductor layer so as to define recessed portions of the semiconductor layer and epitaxially forming raised source/drain regions on the recessed portions of the semiconductor layer.Type: ApplicationFiled: October 28, 2016Publication date: May 3, 2018Inventors: Marcel Richter, Ardechir Pakfar, Armin Muehlhoff
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Patent number: 9184260Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. First sidewall spacers are formed adjacent to sidewalls of the gate electrode structure, and the first sidewall spacers include a nitride. An oxide etchant is applied to a surface of the semiconductor substrate after forming the first sidewall spacers. A second spacer material that includes a nitride is deposited over the semiconductor substrate and the first sidewall spacers to form a second spacer layer after applying the oxide etchant to the surface of the semiconductor substrate. The second spacer layer is etched with a second spacer etchant to form second sidewall spacers.Type: GrantFiled: November 14, 2013Date of Patent: November 10, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Joanna Wasyluk, Dominic Thurmer, Ardechir Pakfar, Markus Lenski
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Patent number: 9177874Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an optical planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.Type: GrantFiled: August 28, 2013Date of Patent: November 3, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Joachim Patzer, Ardechir Pakfar, Dominic Thurmer, Chih-Chun Wang, Remi Riviere, Robert Melzer, Bastian Haussdoerfer, Martin Weisheit
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Patent number: 9034746Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.Type: GrantFiled: October 27, 2014Date of Patent: May 19, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Joachim Patzer, Ardechir Pakfar, Clemens Fitz, Dominic Thurmer
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Publication number: 20150132914Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. First sidewall spacers are formed adjacent to sidewalls of the gate electrode structure, and the first sidewall spacers include a nitride. An oxide etchant is applied to a surface of the semiconductor substrate after forming the first sidewall spacers. A second spacer material that includes a nitride is deposited over the semiconductor substrate and the first sidewall spacers to form a second spacer layer after applying the oxide etchant to the surface of the semiconductor substrate. The second spacer layer is etched with a second spacer etchant to form second sidewall spacers.Type: ApplicationFiled: November 14, 2013Publication date: May 14, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Joanna Wasyluk, Dominic Thurmer, Ardechir Pakfar, Markus Lenski
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Publication number: 20150064812Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an organic planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.Type: ApplicationFiled: August 28, 2013Publication date: March 5, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Joachim Patzer, Ardechir Pakfar, Dominic Thurmer, Chih-Chun Wang, Remi Riviere, Robert Melzer, Bastian Haussdoerfer, Martin Weisheit
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Publication number: 20150044861Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.Type: ApplicationFiled: October 27, 2014Publication date: February 12, 2015Inventors: Joachim Patzer, Ardechir Pakfar, Clemens Fitz, Dominic Thurmer
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Patent number: 8906794Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.Type: GrantFiled: August 1, 2013Date of Patent: December 9, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Joachim Patzer, Ardechir Pakfar, Clemens Fitz, Dominic Thurmer
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Publication number: 20140353733Abstract: Semiconductor device structures at advanced technologies are provided, wherein a reliable encapsulation of a gate dielectric is already formed during very early stages of fabrication. In illustrative embodiments, a gate stack is formed over a surface of a semiconductor substrate and a sidewall spacer is formed adjacent to the gate stack for covering sidewall surfaces of the gate stack. An additional thin layer is formed over the sidewall spacer, the gate stack and the surface of the semiconductor substrate, and thereafter source/drain extension regions are implanted through the additional thin layer into the substrate in alignment with the sidewall spacer.Type: ApplicationFiled: June 4, 2013Publication date: December 4, 2014Inventors: Gabriela Dilliway, Dina H. Triyoso, Ardechir Pakfar, Markus Lenski, Dominic Thurmer
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Patent number: 8815674Abstract: One method disclosed includes forming a sidewall spacer proximate a gate structure, forming a sacrificial layer of material above a protective cap layer, the sidewall spacer and a substrate, forming a sacrificial protection layer above the sacrificial layer, reducing a thickness of the sacrificial protection layer such that its upper surface is positioned at a level that is below the upper surface of the protective cap layer, performing a first etching process to remove a portion of the sacrificial layer and thereby expose the protective cap layer for further processing, performing a wet acid etching process that includes diluted HF acid in the etch chemistry to remove the protective cap layer and performing at least one process operation to remove at least one of the reduced-thickness sacrificial protection layer or the sacrificial layer from above the surface of the substrate.Type: GrantFiled: February 4, 2014Date of Patent: August 26, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Berthold Reimer, Markus Lenski, Bastian Haussdoerfer, Ardechir Pakfar
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Publication number: 20140227869Abstract: One method disclosed includes forming a sidewall spacer proximate a gate structure, forming a sacrificial layer of material above a protective cap layer, the sidewall spacer and a substrate, forming a sacrificial protection layer above the sacrificial layer, reducing a thickness of the sacrificial protection layer such that its upper surface is positioned at a level that is below the upper surface of the protective cap layer, performing a first etching process to remove a portion of the sacrificial layer and thereby expose the protective cap layer for further processing, performing a wet acid etching process that includes diluted HF acid in the etch chemistry to remove the protective cap layer and performing at least one process operation to remove at least one of the reduced-thickness sacrificial protection layer or the sacrificial layer from above the surface of the substrate.Type: ApplicationFiled: February 4, 2014Publication date: August 14, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Berthold Reimer, Markus Lenski, Bastian Haussdoerfer, Ardechir Pakfar