Patents by Inventor Ardis Liang

Ardis Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11055840
    Abstract: To evaluate a semiconductor-fabrication process, a semiconductor wafer is obtained that includes die grouped into modulation sets. Each modulation set is fabricated using distinct process parameters. The wafer is optically inspected to identify defects. A nuisance filter is trained to classify the defects as DOI or nuisance defects. Based on results of the training, a first, preliminary process window for the wafer is determined and die structures having DOI are identified in a first group of modulation sets bordering the first process window. The trained nuisance filter is applied to the identified defects to determine a second, revised process window for the wafer. A third, further revised process window for the wafer is determined based on SEM images of specified care areas in one or more modulation sets within the second, revised process window. A report is generated that specifies the third process window.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: July 6, 2021
    Assignee: KLA Corporation
    Inventors: Ardis Liang, Martin Plihal, Saravanan Paramasivam, Niveditha Lakshmi Narasimhan, Sandeep Bhagwat
  • Publication number: 20210042908
    Abstract: To evaluate a semiconductor-fabrication process, a semiconductor wafer is obtained that includes die grouped into modulation sets. Each modulation set is fabricated using distinct process parameters. The wafer is optically inspected to identify defects. A nuisance filter is trained to classify the defects as DOI or nuisance defects. Based on results of the training, a first, preliminary process window for the wafer is determined and die structures having DOI are identified in a first group of modulation sets bordering the first process window. The trained nuisance filter is applied to the identified defects to determine a second, revised process window for the wafer. A third, further revised process window for the wafer is determined based on SEM images of specified care areas in one or more modulation sets within the second, revised process window. A report is generated that specifies the third process window.
    Type: Application
    Filed: September 25, 2019
    Publication date: February 11, 2021
    Inventors: Ardis Liang, Martin Plihal, Saravanan Paramasivam, Niveditha Lakshmi Narasimhan, Sandeep Bhagwat
  • Patent number: 10209628
    Abstract: A method for automatically classifying one or more defects based on electrical design properties includes receiving one or more images of a selected region of a sample, receiving one or more sets of design data associated with the selected region of the sample, locating one or more defects in the one or more images of the selected region of the sample by comparing the one or more images of the selected region of the sample to the one or more sets of design data, retrieving one or more patterns of interest from the one or more sets of design data corresponding to the one or more defects, and classifying the one or more defects in the one or more images of the selected region of the sample based on one or more annotated electrical design properties included in the one or more patterns of interest.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: February 19, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Prasanti Uppaluri, Thirupurasundari Jayaraman, Ardis Liang, Srikanth Kandukuri, Sagar Kekare
  • Patent number: 9835566
    Abstract: Methods and systems for generating inspection results for a specimen with an adaptive nuisance filter are provided. One method includes selecting a portion of events detected during inspection of a specimen having values for at least one feature of the events that are closer to at least one value of at least one parameter of the nuisance filter than the values for at least one feature of another portion of the events. The method also includes acquiring output of an output acquisition subsystem for the sample of events, classifying the events in the sample based on the acquired output, and determining if one or more parameters of the nuisance filter should be modified based on results of the classifying. The nuisance filter or the modified nuisance filter can then be applied to results of the inspection of the specimen to generate final inspection results for the specimen.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: December 5, 2017
    Assignee: KLA-Tencor Corp.
    Inventors: Ardis Liang, Martin Plihal, Raghav Babulnath, Sankar Venkataraman
  • Publication number: 20170344695
    Abstract: A method for automatically classifying one or more defects based on electrical design properties includes receiving one or more images of a selected region of a sample, receiving one or more sets of design data associated with the selected region of the sample, locating one or more defects in the one or more images of the selected region of the sample by comparing the one or more images of the selected region of the sample to the one or more sets of design data, retrieving one or more patterns of interest from the one or more sets of design data corresponding to the one or more defects, and classifying the one or more defects in the one or more images of the selected region of the sample based on one or more annotated electrical design properties included in the one or more patterns of interest.
    Type: Application
    Filed: October 4, 2016
    Publication date: November 30, 2017
    Inventors: Prasanti Uppaluri, Thirupurasundari Jayaraman, Ardis Liang, Srikanth Kandukuri, Sagar Kekare
  • Publication number: 20160258879
    Abstract: Methods and systems for generating inspection results for a specimen with an adaptive nuisance filter are provided. One method includes selecting a portion of events detected during inspection of a specimen having values for at least one feature of the events that are closer to at least one value of at least one parameter of the nuisance filter than the values for at least one feature of another portion of the events. The method also includes acquiring output of an output acquisition subsystem for the sample of events, classifying the events in the sample based on the acquired output, and determining if one or more parameters of the nuisance filter should be modified based on results of the classifying. The nuisance filter or the modified nuisance filter can then be applied to results of the inspection of the specimen to generate final inspection results for the specimen.
    Type: Application
    Filed: March 1, 2016
    Publication date: September 8, 2016
    Inventors: Ardis Liang, Martin Plihal, Raghav Babulnath, Sankar Venkataraman
  • Patent number: 8204296
    Abstract: Methods for generating a standard reference die for use in a die to standard reference die inspection and methods for inspecting a wafer are provided. One computer-implemented method for generating a standard reference die for use in a die to standard reference die inspection includes acquiring output of an inspection system for a centrally located die on a wafer and one or more dies located on the wafer. The method also includes combining the output for the centrally located die and the one or more dies based on within die positions of the output. In addition, the method includes generating the standard reference die based on results of the combining step.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: June 19, 2012
    Assignee: KLA-Tencor Corp.
    Inventors: Kris Bhaskar, Mark McCord, Santosh Bhattacharyya, Ardis Liang, Richard Wallingford, Hubert Altendorfer, Kais Maayah
  • Publication number: 20100329540
    Abstract: Methods for generating a standard reference die for use in a die to standard reference die inspection and methods for inspecting a wafer are provided. One computer-implemented method for generating a standard reference die for use in a die to standard reference die inspection includes acquiring output of an inspection system for a centrally located die on a wafer and one or more dies located on the wafer. The method also includes combining the output for the centrally located die and the one or more dies based on within die positions of the output. In addition, the method includes generating the standard reference die based on results of the combining step.
    Type: Application
    Filed: September 14, 2010
    Publication date: December 30, 2010
    Applicant: KLA-TENCOR CORPORATION
    Inventors: Kris Bhaskar, Mark McCord, Santosh Bhattacharyya, Ardis Liang, Richard Wallingford, Hubert Altendorfer, Kais Maayah
  • Patent number: 7796804
    Abstract: Methods for generating a standard reference die for use in a die to standard reference die inspection and methods for inspecting a wafer are provided. One computer-implemented method for generating a standard reference die for use in a die to standard reference die inspection includes acquiring output of an inspection system for a centrally located die on a wafer and one or more dies located on the wafer. The method also includes combining the output for the centrally located die and the one or more dies based on within die positions of the output. In addition, the method includes generating the standard reference die based on results of the combining step.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: September 14, 2010
    Assignee: KLA-Tencor Corp.
    Inventors: Kris Bhaskar, Mark McCord, Santosh Bhattacharyya, Ardis Liang, Richard Wallingford, Hubert Altendorfer, Kais Maayah
  • Publication number: 20090041332
    Abstract: Methods for generating a standard reference die for use in a die to standard reference die inspection and methods for inspecting a wafer are provided. One computer-implemented method for generating a standard reference die for use in a die to standard reference die inspection includes acquiring output of an inspection system for a centrally located die on a wafer and one or more dies located on the wafer. The method also includes combining the output for the centrally located die and the one or more dies based on within die positions of the output. In addition, the method includes generating the standard reference die based on results of the combining step.
    Type: Application
    Filed: July 18, 2008
    Publication date: February 12, 2009
    Applicant: KLA-TENCOR CORPORATION
    Inventors: Kris Bhaskar, Mark McCord, Santosh Bhattacharyya, Ardis Liang, Richard Wallingford, Hubert Altendorfer, Kais Maayah
  • Patent number: 7345753
    Abstract: Disclosed are methods and apparatus for facilitating procedures implemented on an analysis tool are provided herein. In one embodiment, an apparatus includes an analyzer module arranged for managing an analyzer tool and causing a high resolution image generated by the analyzer tool to be presented in a display. The apparatus also includes an inspector interface module arranged for simulating an inspector interface in the display. The inspector interface includes features that are available on a corresponding inspection tool, and the inspector interface is based at least in part on defect results from the inspection tool. In one embodiment, the analyzer module executes without knowledge of the inspector interface module and visa versa, and the apparatus includes a synchronization mechanism that knows about these two modules and also is capable of communicating with these two modules.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: March 18, 2008
    Assignee: KLA-Tencor Technologies Corporation
    Inventors: Kris Bhaskar, Ardis Liang, Michael J. Van Riet
  • Publication number: 20060102839
    Abstract: Disclosed are methods and apparatus for facilitating procedures implemented on an analysis tool (e.g., review or metrology tool) are provided herein. In one embodiment, an apparatus for analyzing defects includes an analysis tool arranged for imaging a defect and generating a high resolution image and at least one display device arranged for presenting the high resolution image generated by the analysis tool. The apparatus further includes an analyzer module arranged for managing the analyzer tool and causing the high resolution image generated by the analyzer tool to be presented in the at least one display. The apparatus also includes an inspector interface module arranged for simulating an inspector interface in the at least one display device, wherein the inspector interface includes features that are available on a corresponding inspection tool, and wherein the inspector interface is based at least in part on defect results from the inspection tool.
    Type: Application
    Filed: February 28, 2005
    Publication date: May 18, 2006
    Inventors: Kris Bhaskar, Ardis Liang, Michael Riet