Abstract: Methods and systems for generating a placement plan for one or more virtual machines (VMs) in a computing environment are provided. The method comprises providing, to a computing system, input parameters comprising a current placement for the one or more VMs on one or more hosts in a computing network; a target placement that assigns at least one of the one or more VMs to at least another host in said one or more hosts; and a set of constraints with which both the current placement and the target placement comply.

Abstract: Assigning pins to macro-blocks of an Integrated Circuit (IC) chip is described. The macro-block pin assignments are automatically placed using Constraint Programming (CP) techniques to position the pins on the periphery of a macro-block. Bus-ordering and pin-spacing constraints are performed considering all the nets forming the IC design simultaneously. The CP formulation includes modeling detailed and discrete constraints required to achieve an optimal pin-assignment. A stochastic CSP solver is used to define the cost function on search points giving full assignments to all the variables. The macro-block pins are ultimately moved to computed locations.

Abstract: Methods and systems for generating a placement plan for one or more virtual machines (VMs) in a computing environment are provided. The method comprises providing, to a computing system, input parameters comprising a current placement for the one or more VMs on one or more hosts in a computing network; a target placement that assigns at least one of the one or more VMs to at least another host in said one or more hosts; and a set of constraints with which both the current placement and the target placement comply.

Abstract: Assigning pins to macro-blocks of an Integrated Circuit (IC) chip is described. The macro-block pin assignments are automatically placed using Constraint Programming (CP) techniques to position the pins on the periphery of a macro-block. Bus-ordering and pin-spacing constraints are performed considering all the nets forming the IC design simultaneously. The CP formulation includes modeling detailed and discrete constraints required to achieve an optimal pin-assignment. A stochastic CSP solver is used to define the cost function on search points giving full assignments to all the variables. The macro-block pins are ultimately moved to computed locations.

Abstract: Test generation is improved by learning the relationship between an initial state vector for a stimuli generator and generation success. A stimuli generator for a design-under-verification is provided with information about the success probabilities of potential assignments to an initial state bit vector. Selection of initial states according to the success probabilities ensures a higher success rate than would be achieved without this knowledge. The approach for obtaining an initial state bit vector employs a CSP solver. A learning system is directed to model the behavior of possible initial state assignments. The learning system develops the structure and parameters of a Bayesian network that describes the relation between the initial state and generation success.

Abstract: Test generation is improved by learning the relationship between an initial state vector for a stimuli generator and generation success. A stimuli generator for a design-under-verification is provided with information about the success probabilities of potential assignments to an initial state bit vector. Selection of initial states according to the success probabilities ensures a higher success rate than would be achieved without this knowledge. The approach for obtaining an initial state bit vector employs a CSP solver. A learning system is directed to model the behavior of possible initial state assignments. The learning system develops the structure and parameters of a Bayesian network that describes the relation between the initial state and generation success.