Abstract: Disclosed is a pixel element comprising a semiconductor substrate, a primary charge-collection node, a peripheral node, a modulating node, a circuitry and a backside conductive layer. The semiconductor substrate is configured to convert a flux of photons to first and second conductivity-type mobile charges. The peripheral node at least partially surrounds the primary charge-collection node, which at least partially surrounds the modulating node. The circuitry is used to connect and disconnect a reset voltage to/from the primary charge-collection node, provide a peripheral node voltage to the peripheral node, and measure an amount of the first conductivity-type mobile charges collected by the primary charge-collection node. The modulating node is electrically connected to a modulating voltage source, which is independent of the peripheral node voltage.

Abstract: It is an objective to provide timing event detection. According to a first aspect, a device, comprises: a clocked conditional buffer configured to set an output of the clocked conditional buffer to a first state during a non-detection period; the clocked conditional buffer further configured to toggle the output from the first state to the second state during a detection period, wherein the toggling being enabled by either one of the two states; and the clocked conditional buffer further configured to guarantee that the output is toggling only to one direction during the detection period. This may prevent false event detections. Furthermore, with respect to a timing point of view, one is able to operate without pulses, where pulse width may be difficult to manage in low voltages.

Abstract: Disclosed is a pixel element comprising a semiconductor substrate, a primary charge-collection node, a peripheral node, a modulating node, a circuitry and a backside conductive layer. The semi-conductor substrate is configured to convert a flux of photons to first and second conductivity-type mobile charges. The peripheral node at least partially surrounds the primary charge-collection node, which at least partially surrounds the modulating node. The circuitry is used to connect and disconnect a reset voltage to/from the primary charge-collection node, provide a peripheral node voltage to the peripheral node, and measure an amount of the first conductivity-type mobile charges collected by the primary charge- collection node. The modulating node is electrically connected to a modulating voltage source, which is independent of the peripheral node voltage.

Abstract: A sequential circuit with timing event detection is disclosed. The sequential circuit has an input that is asserted to the output during the second clock phase of a two phase clock signal. A timing event detector is coupled to the sequential element input to assert a timing event signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase.

Abstract: According to the invention, only one type of enhancement MOS transistor type is used in implementing typical Boolean functions in hardware. Preferably, the MOS transistor type allows back bias control for adjusting and compensating the operation conditions. When implemented in PMOS only transistors, the pull-down functionality is performed by a single transistor with its gate and source connected to the output. This type of connection ensures that the pull-down functionality is performed by the leakage current of the pull-down transistor. The leakage currents of all the pull-up transistors need to be smaller than this pull-down current when all the pull-up paths are off. The ratio of these off-currents can be adjusted by the aspect ratios of the transistors. The logic type offers extremely low current consumption with low voltages and offers the possibility to avoid more complex shut-down circuitry often used in ultra low-power designs.

Abstract: A sequential circuit with timing event detection is disclosed. The sequential circuit has an input that is asserted to the output during the second clock phase of a two phase clock signal. A timing event detector is coupled to the sequential element input to assert a timing event signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase.

Abstract: An apparatus for determining information indicative of cardiac malfunctions and abnormalities includes a processing device (502) configured to detect amplitude variation from a signal indicative of cardiovascular motion, where the amplitude variation element variation of the amplitude of a wave pattern, e.g. the AO-peak, repeating on the heart-beat rate on the signal. The processing device is configured to determine, at least partly on the basis of the detected amplitude variation, an indicator of cardiac malfunction and abnormality.

Abstract: A level shifter comprises a first control switch (207) for connecting an output terminal to a first supply voltage (VDDH) to set an output signal to be high, and a second control switch (208) for connecting the output terminal to a signal ground (GND) to set the output signal to be low. The level shifter comprises a pre-charging switch (210) for connecting the output terminal to the first supply voltage, and an input gate circuit (211) for controlling an ability of an input signal to control the second control switch. The level shifter comprises a keeper circuit (212) for controlling the first control switch based on the output signal. The first control switch is controlled with the first supply voltage when the output signal is low, and with a second supply voltage that is between the first supply voltage and the signal ground when the output signal is high.

Abstract: According to the invention, only one type of enhancement MOS transistor type is used in implementing typical Boolean functions in hardware. Preferably, the MOS transistor type allows back bias control for adjusting and compensating the operation conditions. When implemented in PMOS only transistors, the pull-down functionality is performed by a single transistor with its gate and source connected to the output, This type of connection ensures that the pull-down functionality is performed by the leakage current of the pull-down transistor. The leakage currents of all the pull-up transistors need to be smaller than this pull-down current when all the pull-up paths are off. The ratio of these off-currents can be adjusted by the aspect ratios of the transistors. The logic type offers extremely low current consumption with low voltages and offers the possibility to avoid more complex shut-down circuitry often used in ultra low-power designs.

Abstract: A level shifter comprises a first control switch (207) for connecting an output terminal to a first supply voltage (VDDH) to set an output signal to be high, and a second control switch (208) for connecting the output terminal to a signal ground (GND) to set the output signal to be low. The level shifter comprises a pre-charging switch (210) for connecting the output terminal to the first supply voltage, and an input gate circuit (211) for controlling an ability of an input signal to control the second control switch. The level shifter comprises a keeper circuit (212) for controlling the first control switch based on the output signal. The first control switch is controlled with the first supply voltage when the output signal is low, and with a second supply voltage that is between the first supply voltage and the signal ground when the output signal is high.

Abstract: An apparatus for determining information indicative of cardiac malfunctions and abnormalities includes a processing device (402) configured to extract, from a signal indicative of electromagnetic phenomena related to cardiac activity, a first wave pattern repeating on a heart-beat rate and, from a signal indicative of cardiovascular motion, a second wave pattern repeating on the heart-beat rate. The processing device is configured to form timing data such that each timing value of the timing data is indicative of a time period from a reference point of the first wave pattern belonging to one heart-beat period to a reference point of the second wave pattern belonging to the same heart-beat period. The processing device is configured to determine, at least partly on the basis of the timing data, an indicator of cardiac malfunction and abnormality.

Abstract: An apparatus for determining information indicative of cardiac malfunctions and abnormalities includes a processing device (402) configured to extract, from a signal indicative of electromagnetic phenomena related to cardiac activity, a first wave pattern repeating on a heart-beat rate and, from a signal indicative of cardiovascular motion, a second wave pattern repeating on the heart-beat rate. The processing device is configured to form timing data such that each timing value of the timing data is indicative of a time period from a reference point of the first wave pattern belonging to one heart-beat period to a reference point of the second wave pattern belonging to the same heart-beat period. The processing device is configured to determine, at least partly on the basis of the timing data, an indicator of cardiac malfunction and abnormality.

Abstract: An apparatus for determining information indicative of cardiac malfunctions and abnormalities includes a processing device (502) configured to detect amplitude variation from a signal indicative of cardiovascular motion, where the amplitude variation element variation of the amplitude of a wave pattern, e.g. the AO-peak, repeating on the heart-beat rate on the signal. The processing device is configured to determine, at least partly on the basis of the detected amplitude variation, an indicator of cardiac malfunction and abnormality.

Abstract: The present invention relates to differential, locally updating Viterbi decoder characterized in that it contains connection management block (802, 810, 812) which enables decoding a bit per cycle by trellis diagram uniting (810) and distributing procedure (812). Furthermore, the invention is also characterized in that it contains a path metric update block, in which the monotonical growth of state metrics is avoided by a bounding procedure in a path metric update (808).

Abstract: A processor, a circuit and a method for processing images in an analog parallel processor network. A processor comprises a plurality of circuits, a bias transistor and an output transistor. A circuit comprises a first transistor and a second transistor, which receive respective supply voltages and operate as current sources, providing an output voltage. A circuit further comprises a coefficient coupling, which receives the output voltage provided by the first transistor and the second transistor, providing a switching function for a circuit output current. A transistor in a coefficient coupling determines a mode of operation based on the output voltage, provided by the first transistor and the second transistor, and an input current. The circuit provides an output current of the circuit for further processing.

Abstract: A processor, a circuit and a method for processing images in an analog parallel processor network. A processor comprises a plurality of circuits, a bias transistor and an output transistor. A circuit comprises a first transistor and a second transistor, which receive respective supply voltages and operate as current sources, providing an output voltage. A circuit further comprises a coefficient coupling, which receives the output voltage provided by the first transistor and the second transistor, providing a switching function for a circuit output current. A transistor in a coefficient coupling determines a mode of operation based on the output voltage, provided by the first transistor and the second transistor, and an input current. The circuit provides an output current of the circuit for further processing.

Abstract: The invention pertains to a method and corrector (IC6) for correcting an error in a parallel analog-to-digital conversion. Such a correctable error is caused by uncertainties in the reading of the states of parallel comparing elements (IC1, IC2, IC3, IC4) in the converter, said uncertainties being brought about by nonideality, such as non-simultaneous state latching. This error is corrected using a nonlinear cellular neural network preferably such that the real level of the phenomenon compared by means of comparing elements (IC1, IC2, IC3, IC4) is estimated by estimating the states corresponding to correct reading of the comparing elements (IC1, IC2, IC3, IC4) read temporally or otherwise erroneously.