Abstract: A digital to analog converter which produces a non-return to zero output voltage. Two SIN DAC converters having return to zero (RZ) output voltages connected to provide a common NRZ output signal. The SIN DAC converters receive the digital signal and a delayed version of the digital signal. The reference sine voltage applied to each SIN DAC have a respective phase shift so that the outputs from each SIN DAC are phase shifted. The combined phase shifted output signals produce an NRZ signal with a reduced susceptibility to clock signal jitter, and which contain significantly less high frequency content than the RZ output signal from a SIN DAC.

Abstract: A continuous time delta-sigma analog to digital converter is disclosed. A summing junction receives an input analog signal to be digitized and a feedback signal. A loop filter receives the combined signals from the summing junction, and a course analog to digital converter converts the combined signal to a multi-bit digital number. A sin DAC provides a feedback signal to the summing junction, by reconverting the multi-bit digital signal to an analog signal. The sin DAC produces a linear output signal having a reduced phase jitter, resulting in a lower noise floor for the multi-digital signal. The sin DAC may be an NRZ sin DAC which avoids stringent linearity requirements on the summing junction.

Abstract: A digital to analog converter which produces a non-return to zero output voltage. Two SIN DAC converters having return to zero (RZ) output voltages connected to provide a common NRZ output signal. The SIN DAC converters receive the digital signal and a delayed version of the digital signal. The reference sine voltage applied to each SIN DAC have a respective phase shift so that the outputs from each SIN DAC are phase shifted. The combined phase shifted output signals produce an NRZ signal with a reduced susceptibility to clock signal jitter, and which contain significantly less high frequency content than the RZ output signal from a SIN DAC.

Abstract: A continuous time delta-sigma analog to digital converter is disclosed. A summing junction receives an input analog signal to be digitized and a feedback signal. A loop filter receives the combined signals from the summing junction, and a course analog to digital converter converts the combined signal to a multi-bit digital number. A sin DAC provides a feedback signal to the summing junction, by reconverting the multi-bit digital signal to an analog signal. The sin DAC produces a linear output signal having a reduced phase jitter, resulting in a lower noise floor for the multi-digital signal. The sin DAC may be an NRZ sin DAC which avoids stringent linearity requirements on the summing junction.

Abstract: A sigma delta modulation device and method for filtering high frequency intermediate frequency signals. A summing amplifier receives the analog intermediate frequency signal, and provides to a surface acoustic wave filter (SAW) an analog signal which is to be converted to a digital quantity. A quantizer digitizes the signal to produce a digitized intermediate frequency signal. A digital to analog converter provides a feedback signal from the quantizer output signal, to the summing amplifier to form a sigma delta modulation device. The SAW filter provides for high stop band attenuation of signal images within the intermediate frequency signal, and produces a low noise signal with substantially no intermodulation products.