Patents by Inventor Ariana E. Bondoc

Ariana E. Bondoc has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250379149
    Abstract: Selective metal capping and/or liner materials and processes described herein may enable hermetically encapsulating metal interconnects and metal-silicon interfaces in transistor contacts. In one example, an IC structure includes an interconnect layer with a conductive interconnect that is lined with a ruthenium-based liner, and capped with a selectively deposited cap that includes one or more of ruthenium, molybdenum, tungsten, rhodium, iridium, rhenium, and niobium individually or in an alloy. In another example, an IC structure includes a transistor contact structure with a selectively deposited conductive cap over an interface material, where the conductive cap material is absent or substantially thinner on sidewalls of the contact opening. In one example, the conductive cap material over the Si-metal interface includes one or more of ruthenium, molybdenum, tungsten, rhodium, iridium, platinum, rhenium, cobalt, and niobium individually or in combination.
    Type: Application
    Filed: June 6, 2024
    Publication date: December 11, 2025
    Applicant: Intel Corporation
    Inventors: Christopher J. Jezewski, Abinasha Kalita, Ariana E. Bondoc, Jiun-Ruey Chen, Scott Semproni, Indrani Biswas, Collin Borla, Matthew V. Metz, Akm Shaestagir Chowdhury
  • Publication number: 20250324697
    Abstract: Disclosed herein are IC structures and devices that aim to mitigate proximity effects of deep trench vias. An example IC structure may include a device region having a first face and a second face, the second face being opposite the first face, and further include a conductive via extending between the first face and the second face, wherein the conductive via includes an electrically conductive material, and wherein a concentration of titanium at sidewalls of the conductive via is below about 1015 atoms per cubic centimeter.
    Type: Application
    Filed: June 27, 2025
    Publication date: October 16, 2025
    Inventors: Avijit Barik, Tao Chu, Minwoo Jang, Tofizur RAHMAN, Conor P. Puls, Ariana E. Bondoc, Diane Lancaster, Chi-Hing Choi, Derek Keefer
  • Publication number: 20250098249
    Abstract: Disclosed herein are IC structures and devices that aim to mitigate proximity effects of deep trench vias. An example IC structure may include a device region having a first face and a second face, the second face being opposite the first face, and further include a conductive via extending between the first face and the second face, wherein the conductive via includes an electrically conductive material, and wherein a concentration of titanium at sidewalls of the conductive via is below about 1015 atoms per cubic centimeter.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 20, 2025
    Applicant: Intel Corporation
    Inventors: Avijit Barik, Tao Chu, Minwoo Jang, Tofizur RAHMAN, Conor P. Puls, Ariana E. Bondoc, Diane Lancaster, Chi-Hing Choi, Derek Keefer