Patents by Inventor Arie Ben-Ephraim

Arie Ben-Ephraim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6205546
    Abstract: A computer and a method are described having multiple pointers for a branch instruction. A branch target instruction called by the branch instruction is divided into H parts locatable by K pointers. L of the K pointers are stored in the branch instruction and K-L pointers are stored with the H parts of the branch target instruction. A tag identifies a variable boundary between first and second halves of the memory, word by word. The first half of the memory space contains V of H parts of the instructions and the second half of the memory space contains the H-V parts. The parts in the first and second halves of the memory space are compressed and decompressed in parallel.
    Type: Grant
    Filed: March 22, 1999
    Date of Patent: March 20, 2001
    Assignee: Motorola Inc.
    Inventors: Rami Natan, Arie Ben-Ephraim, Arie Kazachin, Alex Miretsky, Vitaly Sukonik
  • Patent number: 6202144
    Abstract: A computer system and method are described having a single pointer for a branch target instruction and multiple pointers and instruction parts for non-branch target instructions. All instructions, except branch target instructions are divided and stored in different location within a memory. A tag is used to identify a variable boundary between first and second halves of the memory space, word by word. The first half of the memory space contains V of H parts of the instructions and the second half of the memory space contains the H-V parts. The parts in the first and second halves of the memory space can be compressed and decompressed in parallel.
    Type: Grant
    Filed: March 22, 1999
    Date of Patent: March 13, 2001
    Assignee: Motorola Inc.
    Inventors: Arie Ben-Ephraim, Avi Ginsberg, Alex Miretsky, Vitaly Sukonik, Arie Kazachin
  • Patent number: 6178491
    Abstract: A compiler system (190) stores a data structure (101, e.g., a program) to a memory (110) of an execution system (100). The data structure (101) comprises, for example, processor instructions coded by compressed portions of variable lengths. The compiler system (190) partitions some or all memory lines (115) of the memory (110) into P≧2 partitions, e.g., &agr; and &bgr;, and writes code portions A to a first partition (e.g., &agr;) and second code portions B to a second partition (e.g., &bgr;) of an adjacent memory line (115). The compiler system (190) also stores addresses for some or all of the code portions in, for example, the memory (110). The addresses (260) have pointers (a and b) which indicate start positions (jA and jB) for portions A and B. Optionally, pointer magnitudes distinguish portion-to-pointer relations without the need for further identification bits.
    Type: Grant
    Filed: March 22, 1999
    Date of Patent: January 23, 2001
    Assignee: Motorola Inc.
    Inventors: Arie Ben-Ephraim, Vitaly Sukonik, Avi Ginsberg, Alexandre Saper, Alex Miretsky