Patents by Inventor Arie Narkis

Arie Narkis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10140210
    Abstract: An apparatus and method for determining whether data needed for one or more operations is stored in a cache and scheduling the operations for execution based on the determination. For example, one embodiment of a processor comprises: a hierarchy of cache levels for caching data including at least a level 1 (L1) cache; cache occupancy determination logic to determine whether data associated with one or more subsequent operations is stored in one of the cache levels; and scheduling logic to schedule execution of the subsequent operations based on the determination of whether data associated with the subsequent operations is stored in the cache levels.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: November 27, 2018
    Assignee: Intel Corporation
    Inventors: Ayal Zaks, Robert Valentine, Arie Narkis
  • Patent number: 9691117
    Abstract: Data may be streamed out of a graphics pipeline during run time without preprogramming the stream out. A command stream may be captured, draw commands monitored, and shader output definitions may be parsed to determine how to stream out shader data, for example for debugging. Data may be streamed out from an application without using the application's original code.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventor: Arie Narkis
  • Publication number: 20150097846
    Abstract: Data may be streamed out of a graphics pipeline during run time without preprogramming the stream out. A command stream may be captured, draw commands monitored, and shader output definitions may be parsed to determine how to stream out shader data, for example for debugging.
    Type: Application
    Filed: November 30, 2011
    Publication date: April 9, 2015
    Inventors: Gil Fridman, Arie Narkis
  • Publication number: 20150089139
    Abstract: An apparatus and method for determining whether data needed for one or more operations is stored in a cache and scheduling the operations for execution based on the determination. For example, one embodiment of a processor comprises: a hierarchy of cache levels for caching data including at least a level 1 (L1) cache; cache occupancy determination logic to determine whether data associated with one or more subsequent operations is stored in one of the cache levels; and scheduling logic to schedule execution of the subsequent operations based on the determination of whether data associated with the subsequent operations is stored in the cache levels.
    Type: Application
    Filed: September 24, 2013
    Publication date: March 26, 2015
    Inventors: Ayal Zaks, Robert Valentine, Arie Narkis
  • Patent number: 8325182
    Abstract: Methods and systems to sample a subset of primitives from a batch of primitives for cull/no-cull decisions, and to selectively perform a batch-cull operation on the batch of primitives in response to cull/no-cull decisions of the samples. Cull/no-cull decisions may be determined in response to one or more of a sign and magnitude of a z-component of a surface normal to corresponding primitives, using one or more primitive-independent, vertex-based cull codes, which may include a cull code based on 2-dimensional pixel space positions corresponding to the primitives. 2-dimensional pixel space positions may be pre-computed for vertices associated with a batch of primitives in advance of sampling culling.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: December 4, 2012
    Assignee: Intel Corporation
    Inventors: Uzi Sarel, Arie Narkis
  • Publication number: 20100164969
    Abstract: Methods and systems to sample a subset of primitives from a batch of primitives for cull/no-cull decisions, and to selectively perform a batch-cull operation on the batch of primitives in response to cull/no-cull decisions of the samples. Cull/no-cull decisions may be determined in response to one or more of a sign and magnitude of a z-component of a surface normal to corresponding primitives, using one or more primitive-independent, vertex-based cull codes, which may include a cull code based on 2-dimensional pixel space positions corresponding to the primitives. 2-dimensional pixel space positions may be pre-computed for vertices associated with a batch of primitives in advance of sampling culling.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Inventors: Uzi Sarel, Arie Narkis