Abstract: This invention provides novel methods for the detection of chitinous contaminants of non-chitinous biological materials. The methods are accurate, highly reproducible, rapid and relatively inexpensive. The methods are well suited to commercial applications, particularly in the food and agriculture industry where biological materials (e.g. food products) are regularly screened for contaminants (e.g. insect, mold, fungus, etc.). In one embodiment, the methods involve contacting a biological sample with a probe that is a lectin that binds chitin, contacting the sample with a pectinase; and detecting binding of said lectin to a chitin where the binding indicates the presence of chitin in the biological sample.

Abstract: This invention relates to magnetic separators for magnetically separating different components of a test sample. The magnetic separators can be used in methods of separating cells.

Abstract: An apparatus comprising a transmit portion and a receive portion. The transmit portion may be configured to present (i) one or more data signals and (ii) a configuration signal, in response to one or more input signals. The receive portion may be configured to receive (i) all of the one or more data signals when operating in a first mode and (ii) less than all of the data signals when operating in a second mode. The first and second modes may be configured in response to the configuration signal.

Abstract: An apparatus comprising a translator circuit and a cache. The translator circuit may be configured to (i) translate one or more first instruction codes of a first instruction set into second instruction codes of a second instruction set, (ii) present the second instruction codes to a processor, and (iii) allow interrupts to the processor to be handled seamlessly.

Abstract: An apparatus comprising a circuit configured to (i) translate one or more instruction codes of a first instruction set into a sequence of instruction codes of a second instruction set and (ii) present the sequence of instruction codes of the second instruction set in response to a predetermined number of addresses.

Abstract: An apparatus comprising one or more first processors and one or more second processors. The one or more first processors may each comprise a first random access memory (RAM) sections. The one or more second processors may each comprise a read only memory (ROM) section and a second RAM section. The one or more first processors may be configured to operate in either (i) a first mode that executes code stored in the one or more ROM sections or (ii) a second mode that processes code stored in the one or more first RAM sections. The one or more second processors may be configured to execute code from either (i) the one or more ROM sections or (ii) the one or more second RAM sections. The apparatus may provide interoperability that may increase system observability and decrease system debugging complexity.

Abstract: A programmable network element (400) operates on packet traffic flowing through the element in accordance with a gateway program (404, 405, 406) which is dynamically uploaded into the network element or unloaded from it via a mechanism separate from the actual packet traffic as the element operates. Such programmable network element can simultaneously operate on plural packet flows with different or the same programs being applied to each flow. A dispatcher (402) provides a packet filter (403) with a set of rules provided by one or more of the dynamically loaded and invoked programs. These rules define, for each program, the characteristics of those packets flowing through the network element that are to be operated upon in some manner. A packet that flows from the network through the filter and satisfies one or more of such rules is sent by the packet filter to the dispatcher.

Abstract: This invention provides novel methods for the detection of chitinous contaminants of non-chitinous biological materials. The methods are accurate, highly reproducible, rapid and relatively inexpensive. The methods are well suited to commercial applications, particularly in the food and agriculture industry where biological materials (e.g. food products) are regularly screened for contaminants (e.g. insect, mold, fungus, etc.). In one embodiment, the methods involve contacting a biological sample with a probe that is a lectin that binds chitin, contacting the sample with a pectinase; and detecting binding of said lectin to a chitin where the binding indicates the presence of chitin in the biological sample.

Abstract: A method and apparatus for synchronization of an audio/visual bitstream is transmitted by an encoder and received by a decoder by employing duplication or elimination of audio samples and video pixels. The invention enables clock synchronization between the encoder and a decoder with an unregulated clock oscillator so as to control the data reader by skipping ahead (eliminating a data element) or to pause (duplicating a data element) depending on whether the encoder clock is faster or slower than the decoder clock.

Abstract: In order to transparently redirect an HTTP connection request that is directed to an origin server (107) to a proxy cache (110-1), a proxy redirector (104) translates the destination address of packets directed to the origin server to the address of the proxy. During a handshaking procedure, a TCP connection is transparently established between the client (110-1) and the proxy cache. When the client transmits a GET request to what it thinks is the origin server, which request specifies the complete address of an object at that origin server that it wants a copy of, the proxy redirector modifies the complete address specified in that GET request before it is sent to the proxy cache. Specifically, the IP address of the origin server found in the destination field in the IP header of the one or more packets from the client containing the GET request is added by the proxy redirector as a prefix to the complete URL in the GET request to form an absolute URL.

Abstract: An adapter or add-in card for using in a peripheral component interconnect (PCI) computer includes a universal module which couples the card to the PCI bus. The module includes a set of selectively programmable configuration registers which are loaded by a microprocessor on the adapter. A circuit arrangement on the module issues a command which inhibits the PCI processor from accessing the configuration registers until fully loaded.

Abstract: An adapter or add-in card for use in a peripheral component interconnect (PCI) computer includes a universal module which couples the card to the PCI bus. The module includes a set of selectively programmable configuration registers which are loaded by a microprocessor on the adapter. A circuit arrangement on the module issues a command which inhibits the PCI processor from accessing the configuration registers until fully loaded. Another circuit arrangement presents the Expansion ROM base address register as a `read/write` register or a read only register with all bits set to logical "0 " to the PCI computer. If the Expansion ROM base address register is presented as a read only register with all bits set to "0 ", the PCI computer concludes that no Expansion ROM exists on the add-in card, and its contents are not shadowed into the memory of the PCI computer. This disabling of the Expansion ROM causes memory space to be conserved in the computer.

Abstract: An information processing system includes a processor for processing information; a processor bus, a first expansion bus; a host bridge for coupling the processor bus to the first expansion bus; a second expansion bus; a first bus bridge for coupling the first expansion bus to the second expansion bus; a plurality of input/output (I/O) devices coupled to the second expansion bus; and a first storage device for storing a first set of configuration data for the plurality of I/O devices; a second storage device for storing additional configuration data. The first storage device includes a register for storing a pointer for pointing to addresses in the first storage device for forwarding addresses sent from the processor to the I/O devices.