Patents by Inventor Ariel Doubchak
Ariel Doubchak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11387848Abstract: Embodiments of the present disclosure provide a controller hierarchical decoding architecture. For instance, multiple decoder hierarchies are implemented along with use of hierarchies of codes with locality (e.g., larger code length of a hierarchy is composed of local codes from a lower hierarchy). The hierarchical Error Correction Code (ECC) decoding includes multiple hierarchies such as a first hierarchy, a second hierarchy, and additional hierarchies as needed. A first hierarchy includes low-complexity ECC engines, each connected to a NAND channel for computing local codes of low code lengths. A second hierarchy includes higher complexity ECC engines that shares several NAND channels for correcting corrupt data using relatively larger code length (e.g., and the higher complexity ECC engines of the second hierarchy performs decoding operations using more complex decoding algorithms). The larger code length is composed of local codes from a previous hierarchy.Type: GrantFiled: March 11, 2021Date of Patent: July 12, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Amit Berman, Ariel Doubchak
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Publication number: 20220116057Abstract: A machine-learning (ML) error-correcting code (ECC) controller may include a hard-decision (HD) ECC decoder optimized for high-speed data throughput, a soft-decision (SD) ECC decoder optimized for high-correctability data throughput, and a machine-learning equalizer (MLE) configured to variably select one of the HD ECC decoder or the SD ECC decoder for data throughput. An embodiment of the ML ECC controller may provide speed-optimized HD throughput based on a linear ECC. The linear ECC may be a soft Hamming permutation code (SHPC).Type: ApplicationFiled: October 6, 2021Publication date: April 14, 2022Inventors: Ariel DOUBCHAK, Dikla SHAPIRO, Evgeny BLAICHMAN, Lital COHEN, Amit BERMAN
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Publication number: 20220021401Abstract: A method of performing division operations in an error correction code includes the steps of receiving an output ??F†{0} wherein F=GF(2r) is a Galois field of 2r elements, ?=?0?i?r?1?i×?i wherein ? is a fixed primitive element of F, and ?i?GF(2), wherein K=GF(2s) is a subfield of F, and {1, ?} is a basis of F in a linear subspace of K; choosing a primitive element ??K, wherein ?=?1+?×?2, ?1=?0?i?s?1?i×?i?K, ?2=?0?i?s?1?i+s×?i?K, and ?=[?0, . . . , ?r?1]T?GF(2)r; accessing a first table with ?1 to obtain ?3=?1?1, computing ?2×?3 in field K, accessing a second table with ?2=?3 to obtain (1+?×?2×?3)?1=?4+?×?5, wherein ??1=(?1×(1+?×?2×?3))?1=?3×(?4+?×?5)=?3×?4+?×?3×?5; and computing products ?3×?4 and ?3×?5 to obtain ??1=?0?i?s?1?i×?i+?·?i?i?s?1?i+s=?i where ?i?GF(2).Type: ApplicationFiled: July 15, 2020Publication date: January 20, 2022Inventors: AVNER DOR, Amit Berman, Ariel Doubchak, Elik Almog Sheffi, Yaron Shany
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Publication number: 20210376859Abstract: Systems and methods are described for low power error correction coding (ECC) for embedded universal flash storage (eUFS) are described. The systems and methods may include identifying a first element of an algebraic field; generating a plurality of lookup tables for multiplying the first element; multiplying the first element by a plurality of additional elements of the algebraic field, wherein the multiplication for each of the additional elements is performed using an element from each of the lookup tables; and encoding information according to an ECC scheme based on the multiplication.Type: ApplicationFiled: May 28, 2020Publication date: December 2, 2021Inventors: AVNER DOR, Amit Berman, Ariel Doubchak
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Patent number: 11184029Abstract: Systems and methods are described for low power error correction coding (ECC) for embedded universal flash storage (eUFS) are described. The systems and methods may include identifying a first element of an algebraic field; generating a plurality of lookup tables for multiplying the first element; multiplying the first element by a plurality of additional elements of the algebraic field, wherein the multiplication for each of the additional elements is performed using an element from each of the lookup tables; and encoding information according to an ECC scheme based on the multiplication.Type: GrantFiled: May 28, 2020Date of Patent: November 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Avner Dor, Amit Berman, Ariel Doubchak
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Patent number: 11184026Abstract: A memory controller is configured to perform first error correcting code (ECC) encoding on a plurality of first frames of data, generate a plurality of delta syndrome units corresponding, respectively, to the plurality of first frames of data, generate a delta syndrome codeword by performing second ECC encoding on the plurality of delta syndrome units, the delta syndrome codeword including one or more redundancy data units, perform third ECC encoding on at least one second frame of data such that the encoded at least one second frame of data is a first vector of bits, and determine a second vector of bits such that, adding the second vector of bits to the first vector of bits forms a combined vector of bits which is an ECC codeword having a delta syndrome a value of which is pre-fixed based on at least one of the one or more redundancy data units.Type: GrantFiled: March 13, 2019Date of Patent: November 23, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Amit Berman, Ariel Doubchak
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Publication number: 20210344356Abstract: A mobile electronic device may include a memory device and a memory controller including an error correction code (ECC) encoder to encode data, a constrained channel encoder configured to encode an output of the ECC encoder based on one or more constraints, a reinforcement learning pulse programming (RLPP) component configured to identify a programming algorithm for programming the data to the memory device, an expectation maximization (EM) signal processing component configured to receive a noisy multi-wordline voltage vector from the memory device and classify each bit of the vector with a log likelihood ration (LLR) value, a constrained channel decoder configured to receive a constrained vector from the EM signal processing component and produce an unconstrained vector, and an ECC decoder configured to decode the unconstrained vector. A machine learning interference cancellation component may operate based on or independent of input from the EM signal processing component.Type: ApplicationFiled: May 4, 2020Publication date: November 4, 2021Inventors: AMIT BERMAN, ARIEL DOUBCHAK, ELI HAIM, EVGENY BLAICHMAN
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Patent number: 11115055Abstract: A decoding circuit includes a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The BCH decoder includes a Syndrome stage for generating syndromes based on a BCH encoded word, a Berlekamp-Massey (BM) stage performing a Berlekamp-Massey algorithm on the syndromes to generate Error Location Polynomial (ELP) coefficients, a Chien stage that performs a Chien search on the ELP coefficients using a Fast Fourier Transform (FFT) to generate error bits and iteration information, and a Frame Fixer stage configured to reorder the error bits to be sequential based on the iteration information. The BCH decoder decodes the BCH encoded word using the reordered error bits.Type: GrantFiled: January 10, 2019Date of Patent: September 7, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ariel Doubchak, Dikla Shapiro, Amit Berman
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Patent number: 11031956Abstract: A method for storing data within a memory device includes receiving data to be stored. The received data is encoded. The encoded data is stored within the memory device. Encoding the received data includes encoding the data into two or more sub-codewords. Each of the two or more sub-codewords includes a plurality of outer codewords. Two or more of the plurality of outer codewords are grouped to form a larger codeword that is larger than each of the plurality of outer codewords and the larger codeword is constructed to correct errors and/or erasures that are not correctable by the plurality of outer codewords, individually.Type: GrantFiled: June 25, 2019Date of Patent: June 8, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Amit Berman, Ariel Doubchak, Avner Dor
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Patent number: 10922025Abstract: A memory system including a nonvolatile memory (NVM) device and a controller is provided. The NVM device includes a main region and a spare region. The controller writes write data to a selected row of the main region, determines whether the written row is bad, and writes the write data to a spare address in the spare region and writes the spare address to the bad row, when the written row is determined to be bad.Type: GrantFiled: July 17, 2019Date of Patent: February 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Amit Berman, Ariel Doubchak, Noam Livne
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Publication number: 20210019082Abstract: A memory system including a nonvolatile memory (NVM) device and a controller is provided. The NVM device includes a main region and a spare region. The controller writes write data to a selected row of the main region, determines whether the written row is bad, and writes the write data to a spare address in the spare region and writes the spare address to the bad row, when the written row is determined to be bad.Type: ApplicationFiled: July 17, 2019Publication date: January 21, 2021Inventors: AMIT BERMAN, ARIEL DOUBCHAK, NOAM LIVNE
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Publication number: 20200412386Abstract: A method for storing data within a memory device includes receiving data to be stored. The received data is encoded. The encoded data is stored within the memory device. Encoding the received data includes encoding the data into two or more sub-codewords. Each of the two or more sub-codewords includes a plurality of outer codewords. Two or more of the plurality of outer codewords are grouped to form a larger codeword that is larger than each of the plurality of outer codewords and the larger codeword is constructed to correct errors and/or erasures that are not correctable by the plurality of outer codewords, individually.Type: ApplicationFiled: June 25, 2019Publication date: December 31, 2020Inventors: AMIT BERMAN, ARIEL DOUBCHAK, AVNER DOR
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Patent number: 10783970Abstract: A method for performing a write operation in a random access memory (RAM) includes selecting a target block in a RAM with a greatest number of invalid pages, reading valid pages from target block, when a number of invalid pages is greater than a predetermined threshold, performing a bitline-wise block erase of the target block in said RAM, and copying-back valid data to the erased target block in a row-by-row set operation, wherein the erased target block is written with the valid data. Performing the bitline-wise block erase includes sequentially powering on each bitline with a predetermined reset voltage where all other bitlines and wordlines are grounded.Type: GrantFiled: December 12, 2018Date of Patent: September 22, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Amit Berman, Ariel Doubchak, Noam Livne
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Publication number: 20200295783Abstract: A memory controller is configured to perform first error correcting code (ECC) encoding on a plurality of first frames of data, generate a plurality of delta syndrome units corresponding, respectively, to the plurality of first frames of data, generate a delta syndrome codeword by performing second ECC encoding on the plurality of delta syndrome units, the delta syndrome codeword including one or more redundancy data units, perform third ECC encoding on at least one second frame of data such that the encoded at least one second frame of data is a first vector of bits, and determine a second vector of bits such that, adding the second vector of bits to the first vector of bits forms a combined vector of bits which is an ECC codeword having a delta syndrome a value of which is pre-fixed based on at least one of the one or more redundancy data units.Type: ApplicationFiled: March 13, 2019Publication date: September 17, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Amit BERMAN, Ariel DOUBCHAK
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Publication number: 20200228144Abstract: A decoding circuit includes a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The BCH decoder includes a Syndrome stage for generating syndromes based on a BCH encoded word, a Berlekamp-Massey (BM) stage performing a Berlekamp-Massey algorithm on the syndromes to generate Error Location Polynomial (ELP) coefficients, a Chien stage that performs a Chien search on the ELP coefficients using a Fast Fourier Transform (FFT) to generate error bits and iteration information, and a Frame Fixer stage configured to reorder the error bits to be sequential based on the iteration information. The BCH decoder decodes the BCH encoded word using the reordered error bits.Type: ApplicationFiled: January 10, 2019Publication date: July 16, 2020Inventors: ARIEL DOUBCHAK, Dikla Shapiro, Amit Berman
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Publication number: 20200194080Abstract: A method for performing a write operation in a random access memory (RAM) includes selecting a target block in a RAM with a greatest number of invalid pages, reading valid pages from target block, when a number of invalid pages is greater than a predetermined threshold, performing a bitline-wise block erase of the target block in said RAM, and copying-back valid data to the erased target block in a row-by-row set operation, wherein the erased target block is written with the valid data. Performing the bitline-wise block erase includes sequentially powering on each bitline with a predetermined reset voltage where all other bitlines and wordlines are grounded.Type: ApplicationFiled: December 12, 2018Publication date: June 18, 2020Inventors: AMIT BERMAN, Ariel Doubchak, Noam Livne
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Publication number: 20120028648Abstract: A load balancing system for a wireless network comprises: a base station parameter extraction unit able to extract base station availability parameters of currently available base stations; and a base station quality of service selector associated with said base station parameter extraction unit configured to determine from said parameters which of said available base stations is able to provide a currently required quality of service. The system requests resources from one such base station, thereby to ensure that mobile stations are distributed in a balanced manner between the available base stations. As well as quality of service, interference with other links may be taken into account, and uplinks and downlinks may be considered separately.Type: ApplicationFiled: October 10, 2011Publication date: February 2, 2012Applicant: Alvarion Ltd.Inventors: Naftali Chayat, David Zelikovsky, Ariel Doubchak, Nadav Lavi
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Patent number: 8036675Abstract: A load balancing system for a wireless network comprises: a base station parameter extraction unit able to extract base station availability parameters of currently available base stations; and a base station quality of service selector associated with said base station parameter extraction unit configured to determine from said parameters which of said available base stations is able to provide a currently required quality of service. The system requests resources from one such base station, thereby to ensure that mobile stations are distributed in a balanced manner between the available base stations. As well as quality of service, interference with other links may be taken into account, and uplinks and downlinks may be considered separately.Type: GrantFiled: March 31, 2009Date of Patent: October 11, 2011Assignee: Alvarion Ltd.Inventors: Naftali Chayat, David Zelikovsky, Ariel Doubchak, Nadav Lavi
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Patent number: 7970359Abstract: In a wireless transmission system including a transmit delay module, delaying each of at least one copy of a signal by a respective delay, the signal being transmitted over a plurality of carrier frequencies and over at least one beam, the at least one beam exhibiting a beam pattern, the number of copies of the signal corresponding to the number of beams, each the at least one copy being associated with a respective one of the at least one beam, the system further including a beam pattern former, coupled with the transmit delay module, producing a plurality of transmit signals corresponding to the beam pattern, a frequency dependent beam shifter, coupled with the beam pattern former, delaying each of the at least one transmit signal by a respective angular shift delay, thereby applying an angular shift to each of the at least one beam, the angular shift of each of the at least one beam corresponding to at least a respective one of the carrier frequencies, wherein each beam is transmitted with a delay correspoType: GrantFiled: July 29, 2008Date of Patent: June 28, 2011Assignee: Alvarion Ltd.Inventors: Ariel Doubchak, Danny Stopler, Rafael Halfon
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Publication number: 20100248738Abstract: A load balancing system for a wireless network comprises: a base station parameter extraction unit able to extract base station availability parameters of currently available base stations; and a base station quality of service selector associated with said base station parameter extraction unit configured to determine from said parameters which of said available base stations is able to provide a currently required quality of service. The system requests resources from one such base station, thereby to ensure that mobile stations are distributed in a balanced manner between the available base stations. As well as quality of service, interference with other links may be taken into account, and uplinks and downlinks may be considered separately.Type: ApplicationFiled: March 31, 2009Publication date: September 30, 2010Applicant: Alvarion Ltd.Inventors: Naftali CHAYAT, David Zelikosky, Ariel Doubchak, Nadav Lavi