Patents by Inventor ARIEL GUR

ARIEL GUR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System, apparatus and method for configurable control of asymmetric multi-threading (SMT) on a per core basis
    Patent number: 11953962
    Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Daniel J. Ragland, Guy M. Therien, Ankush Varma, Eric J. DeHaemer, David T. Mayo, Ariel Gur, Yoav Ben-Raphael, Mark P. Seconi
  • Apparatuses, methods, and systems for hardware control of processor performance levels
    Patent number: 11899599
    Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: February 13, 2024
    Assignee: INTEL CORPORATION
    Inventors: Eliezer Weissmann, Efraim Rotem, Doron Rajwan, Hisham Abu Salah, Ariel Gur, Guy M. Therien, Russell J. Fenger
  • System, Apparatus And Method For Configurable Control Of Asymmetric Multi-Threading (SMT) On A Per Core Basis
    Publication number: 20230131521
    Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.
    Type: Application
    Filed: December 22, 2022
    Publication date: April 27, 2023
    Inventors: Daniel J. Ragland, Guy M. Therien, Ankush Varma, Eric J. DeHaemer, David T. Mayo, Ariel Gur, Yoav Ben-Raphael, Mark P. Seconi
  • System, apparatus and method for configurable control of asymmetric multi-threading (SMT) on a per core basis
    Patent number: 11579944
    Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: Daniel J. Ragland, Guy M. Therien, Ankush Varma, Eric J. DeHaemer, David T. Mayo, Ariel Gur, Yoav Ben-Raphael, Mark P. Seconi
  • APPARATUSES, METHODS, AND SYSTEMS FOR HARDWARE CONTROL OF PROCESSOR PERFORMANCE LEVELS
    Publication number: 20220179808
    Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.
    Type: Application
    Filed: November 16, 2021
    Publication date: June 9, 2022
    Inventors: Eliezer WEISSMANN, Efraim ROTEM, Doron RAJWAN, Hisham ABU SALAH, Ariel GUR, Guy M. THERIEN, Russell J. FENGER
  • Apparatuses, methods, and systems for hardware control of processor performance levels
    Patent number: 11182315
    Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: November 23, 2021
    Assignee: INTEL CORPORATION
    Inventors: Eliezer Weissmann, Efraim Rotem, Doron Rajwan, Hisham Abu Salah, Ariel Gur, Guy M. Therien, Russell J. Fenger
  • Techniques in phase-lock loop configuration in a computing device
    Patent number: 10958278
    Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Ariel Gur, Daniel J. Ragland, Yoav Ben-Raphael, Ernest Knoll
  • TECHNIQUES IN PHASE-LOCK LOOP CONFIGURATION IN A COMPUTING DEVICE
    Publication number: 20210036708
    Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Ariel Gur, Daniel J. Ragland, Yoav Ben-Raphael, Ernest Knoll
  • Processors, methods, and systems to adjust maximum clock frequencies based on instruction type
    Patent number: 10579125
    Abstract: An integrated circuit of an aspect includes a power control unit having an interface to receive an indication that one or more instructions of a first type are to be performed by a core. The power control unit also has logic to control a maximum clock frequency for the core based on the indication that the instructions of the first type are to be performed by the core.
    Type: Grant
    Filed: February 27, 2016
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Daniel J. Ragland, Pavithra Sampath, Kirk Pfaender, Kahraman D. Akdemir, Ariel Gur
  • System, Apparatus And Method For Configurable Control Of Asymmetric Multi-Threading (SMT) On A Per Core Basis
    Publication number: 20190079806
    Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.
    Type: Application
    Filed: November 14, 2018
    Publication date: March 14, 2019
    Inventors: Daniel J. Ragland, Guy M. Therien, Ankush Varma, Eric J. DeHaemer, David T. Mayo, Ariel Gur, Yoav Ben-Raphael, Mark P. Seconi
  • Method and apparatus for automatic adaptive voltage control
    Patent number: 10095302
    Abstract: A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Ariel Gur, Daniel J Ragland, Ofer Nathan, Nadav Shulman, Esfir Natanzon
  • APPARATUSES, METHODS, AND SYSTEMS FOR HARDWARE CONTROL OF PROCESSOR PERFORMANCE LEVELS
    Publication number: 20180232330
    Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.
    Type: Application
    Filed: February 10, 2017
    Publication date: August 16, 2018
    Inventors: ELIEZER WEISSMANN, EFRAIM ROTEM, DORON RAJWAN, HISHAM ABU SALAH, ARIEL GUR, Guy M. THERIEN, RUSSELL J. FENGER
  • METHOD AND APPARATUS FOR AUTOMATIC ADAPTIVE VOLTAGE CONTROL
    Publication number: 20180059763
    Abstract: A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.
    Type: Application
    Filed: August 29, 2016
    Publication date: March 1, 2018
    Inventors: Ariel Gur, Daniel J Ragland, Ofer Nathan, Nadav Shulman, Esfir Natanzon
  • PROCESSORS, METHODS, AND SYSTEMS TO ADJUST MAXIMUM CLOCK FREQUENCIES BASED ON INSTRUCTION TYPE
    Publication number: 20170249000
    Abstract: An integrated circuit of an aspect includes a power control unit having an interface to receive an indication that one or more instructions of a first type are to be performed by a core. The power control unit also has logic to control a maximum clock frequency for the core based on the indication that the instructions of the first type are to be performed by the core.
    Type: Application
    Filed: February 27, 2016
    Publication date: August 31, 2017
    Applicant: Intel Corporation
    Inventors: DANIEL J. RAGLAND, PAVITHRA SAMPATH, KIRK PFAENDER, KAHRAMAN D. AKDEMIR, ARIEL GUR