Patents by Inventor ARIEL SABBA
ARIEL SABBA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230342156Abstract: Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.Type: ApplicationFiled: April 24, 2023Publication date: October 26, 2023Inventors: Jason W. Brandt, Deepak K. Gupta, Rodrigo Branco, Joseph Nuzman, Robert S. Chappell, Sergiu Ghetie, Wojciech Powiertowski, Jared W. Stark, IV, Ariel Sabba, Scott J. Cape, Hisham Shafi, Lihu Rappoport, Yair Berger, Scott P. Bobholz, Gilad Holzstein, Sagar V. Dalvi, Yogesh Bijlani
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Publication number: 20230315473Abstract: Embodiments of apparatuses and methods for variable-length instruction steering to instruction decode clusters are disclosed. In an embodiment, an apparatus includes a decode cluster and chunk steering circuitry. The decode cluster includes multiple instruction decoders. The chunk steering circuitry is to break a sequence of instruction bytes into a plurality of chunks, create a slice from a one or more of the plurality of chunks based on one or more indications of a number of instructions in each of the one or more of the plurality of chunks, wherein the slice has a variable size and includes a plurality of instructions, and steer the slice to the decode cluster.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Muhammad Azeem, Rangeen Basu Roy Chowdhury, Xiang Zou, Malihe Ahmadi, Joju Joseph Zajo, Ariel Sabba, Ammon Christiansen, Polychronis Xekalakis, Eliyah Kilada
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Patent number: 11635965Abstract: Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.Type: GrantFiled: October 31, 2018Date of Patent: April 25, 2023Assignee: Intel CorporationInventors: Jason W. Brandt, Deepak K. Gupta, Rodrigo Branco, Joseph Nuzman, Robert S. Chappell, Sergiu D. Ghetie, Wojciech Powiertowski, Jared W. Stark, IV, Ariel Sabba, Scott J. Cape, Hisham Shafi, Lihu Rappoport, Yair Berger, Scott P. Bobholz, Gilad Holzstein, Sagar V. Dalvi, Yogesh Bijlani
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Publication number: 20220129763Abstract: An embodiment of an integrated circuit may comprise a front end unit, and circuitry coupled to the front end unit, the circuitry to provide a high confidence, multiple branch offset predictor. For example, the circuitry may be configured to identify an entry in a multiple-taken-branch prediction table that corresponds to a conditional branch instruction, determine if a confidence level of the entry exceeds a threshold confidence level, and, if so determined, provide multiple taken branch predictions that stem from the conditional branch instruction from the entry in the multiple-taken-branch prediction table. Other embodiments are disclosed and claimed.Type: ApplicationFiled: December 22, 2020Publication date: April 28, 2022Applicant: Intel CorporationInventors: Sumeet Bandishte, Jayesh Gaur, Polychronis Xekalakis, Ariel Sabba, Deborah Marr, Sreenivas Subramoney
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Publication number: 20200349312Abstract: An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.Type: ApplicationFiled: April 21, 2020Publication date: November 5, 2020Applicant: Intel CorporationInventors: Tsvika Kurts, Alexander Gendler, Larisa Novakovsky, Anwar Azaarura Zaa'Rura, Afik Sela, Genadi Kazakevich, Alexandra Shainshein, Ariel Sabba
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Publication number: 20200133679Abstract: Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.Type: ApplicationFiled: October 31, 2018Publication date: April 30, 2020Inventors: Jason W. Brandt, Deepak K. Gupta, Rodrigo Branco, Joseph Nuzman, Robert S. Chappell, Sergiu Ghetie, Wojciech Powiertowski, Jared W. Stark, IV, Ariel Sabba, Scott J. Cape, Hisham Shafi, Lihu Rappoport, Yair Berger, Scott P. Bobholz, Gilad Holzstein, Sagar V. Dalvi, Yogesh Bijlani
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Patent number: 10628542Abstract: An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.Type: GrantFiled: July 1, 2017Date of Patent: April 21, 2020Assignee: Intel CorporationInventors: Tsvika Kurts, Alexander Gendler, Larisa Novakovsky, Anwar Azaarura Zaa'Rura, Afik Sela, Genadi Kazakevich, Alexandra Shainshein, Ariel Sabba
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Publication number: 20190213131Abstract: Systems and methods for stream cache memory retrieval include applying a stream cache to predict a sequence of instructions and data across multiple branches. Similar to a conventional computing cache, the stream cache stores and provides data or instructions more quickly than provided by slower data storage media, such as an instruction cache. The stream cache described herein provides the ability to predict instructions and data requests across multiple branches per cycle, and in particular across multiple taken branches per cycle. This stream cache increases instruction supply bandwidth while reducing overall power consumption by saving cycles of the branch predictor structures.Type: ApplicationFiled: January 11, 2018Publication date: July 11, 2019Inventors: Ariel Sabba, Shani Rehana, Michael Tal, Suzan Baransi, Lihu Rappoport, Jared Warner Stark, Franck Sala
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Publication number: 20190005160Abstract: An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.Type: ApplicationFiled: July 1, 2017Publication date: January 3, 2019Inventors: Tsvika Kurts, Alexander Gendler, Larisa Novakovsky, Anwar Azaarura Zaa'Rura, Afik Sela, Genadi Kazakevich, Alexandra Shainshein, Ariel Sabba
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Publication number: 20170149554Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.Type: ApplicationFiled: November 24, 2015Publication date: May 25, 2017Applicant: Intel CorporationInventors: Alexander Gendler, Ernest Knoll, Ofer Nathan, Michael Mishaeli, Krishnakanth V. Sistla, Ariel Sabba, Shani Rehana, Ariel Szapiro, Tsvika Kurts, Ofer Levy
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Patent number: 9660799Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.Type: GrantFiled: November 24, 2015Date of Patent: May 23, 2017Assignee: Intel CorporationInventors: Alexander Gendler, Ernest Knoll, Ofer Nathan, Michael Mishaeli, Krishnakanth V. Sistla, Ariel Sabba, Shani Rehana, Ariel Szapiro, Tsvika Kurts, Ofer Levy
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Patent number: 9471088Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.Type: GrantFiled: June 25, 2013Date of Patent: October 18, 2016Assignee: Intel CorporationInventors: Alexander Gendler, Efraim Rotem, Julius Mandelblat, Alexander Lyakhov, Larisa Novakovsky, George Leifman, Lev Makovsky, Ariel Sabba, Niv Tokman
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Patent number: 9360924Abstract: In an embodiment, a processor includes a plurality of cores and a cache unit reserved for a first core of the plurality of cores. The cache unit may include a first cache slice, a second cache slice, and power logic to switch operation of the cache unit between a first operating mode and a second operating mode. The first operating mode may include use of both the first cache slice and the second cache slice. The second operating mode may include use of the first cache slice and disabling the second cache slice. Other embodiments are described and claimed.Type: GrantFiled: May 29, 2013Date of Patent: June 7, 2016Assignee: Intel CorporationInventors: Alexander Gendler, Larisa Novakovsky, Ariel Sabba, Niv Tokman
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Publication number: 20140380081Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.Type: ApplicationFiled: June 25, 2013Publication date: December 25, 2014Inventors: Alexander Gendler, Efraim Rotem, Julius Mandelblat, Alexander Lyakhov, Larisa Novakovsky, George Leifman, Lev Makovsky, Ariel Sabba, Niv Tokman
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Publication number: 20140359330Abstract: In an embodiment, a processor includes a plurality of cores and a cache unit reserved for a first core of the plurality of cores. The cache unit may include a first cache slice, a second cache slice, and power logic to switch operation of the cache unit between a first operating mode and a second operating mode. The first operating mode may include use of both the first cache slice and the second cache slice. The second operating mode may include use of the first cache slice and disabling the second cache slice. Other embodiments are described and claimed.Type: ApplicationFiled: May 29, 2013Publication date: December 4, 2014Inventors: ALEXANDER GENDLER, LARISA NOVAKOVSKY, ARIEL SABBA, Niv Tokman