Patents by Inventor Ariel Szapiro
Ariel Szapiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11543878Abstract: A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.Type: GrantFiled: May 1, 2018Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Efraim Rotem, Eliezer Weissmann, Eric Dehaemer, Alexander Gendler, Nadav Shulman, Krishnakanth Sistla, Nir Rosenzweig, Ankush Varma, Ariel Szapiro, Arye Albahari, Ido Melamed, Nir Misgav, Vivek Garg, Nimrod Angel, Adwait Purandare, Elkana Korem
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Publication number: 20210208659Abstract: An adaptive or dynamic power virus control scheme (hardware and/or software) that dynamically adjusts maximum dynamic capacitance (CdynMax) and corresponding maximum frequency (POnMax) setting per application executed on a processor core. A power management unit monitors telemetry such as a number of throttled cycles due to CdynMax threshold excursions cycles for the processor core and a cost of average cycle Cdyn cost for the processor core. As the number of throttling cycles increases for the processor core, the aCode firmware of the power management unit decides to increase the Cdyn level or threshold for that core (e.g., to make the threshold less aggressive). As the average Cdyn cost over a number of cycles becomes lower than a threshold, aCode adjusts the threshold to a lower threshold (e.g., more aggressive threshold) and lower Cdyn.Type: ApplicationFiled: March 19, 2021Publication date: July 8, 2021Applicant: Intel CorporationInventors: Alexander Gendler, Adwait Purandare, Ankush Varma, Nazar Haider, Daniela Kaufman, Gilad Bomstein, Shlomo Attias, Amit Gabai, Ariel Szapiro
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Patent number: 11016556Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.Type: GrantFiled: July 16, 2019Date of Patent: May 25, 2021Assignee: Intel CorporationInventors: Alexander Gendler, Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell
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Publication number: 20210064110Abstract: In an embodiment, a processor includes a power control unit, a master processing engine, a set of slave processing engines, and a voltage regulator. The master processing engine is to, in response to a receipt of a change message from the power control unit, control the voltage regulator to adjust a voltage level provided to the master processing engine and the set of slave processing engines. Other embodiments are described and claimed.Type: ApplicationFiled: August 27, 2018Publication date: March 4, 2021Inventors: Alexander Gendler, Krishnakanth V. Sistla, Ankush Varma, Ariel Szapiro
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Publication number: 20210018971Abstract: A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.Type: ApplicationFiled: May 1, 2018Publication date: January 21, 2021Inventors: EFRAIM ROTEM, ELIEZER WEISSMANN, ERIC DEHAEMER, ALEXANDER GENDLER, NADAV SHULMAN, KRISHNAKANTH SISTLA, NIR ROSENZWEIG, ANKUSH VARMA, ARIEL SZAPIRO, ARYE ALBAHARI, IDO MELAMED, NIR MISGAV, VIVEK GARG, NIMROD ANGEL, ADWAIT PURANDARE, ELKANA KOREM
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Patent number: 10809790Abstract: Apparatus and methods are provided for improving yield and frequency performance of integrated circuit processors, such as multiple-core processors. In an example, an apparatus can include a plurality of clock buffers, each clock buffer of the plurality of clock buffers configured to receive a first clock signal and distribute a plurality of second clock signals, a one-time programmable locate critical path mechanism configured provide a plurality of indications to enable or disable a delay of each clock buffer of the plurality of clock buffers, and a power management control circuit configured to over-ride one or more of the plurality of indications in a first non-test mode of operation of the apparatus and to not over-ride the one or more indications in a second non-test mode of operation of the apparatus.Type: GrantFiled: June 30, 2017Date of Patent: October 20, 2020Assignee: Intel CorporationInventors: Yiftach Gilad, Ariel Szapiro, Elkana Korem, Alexander Gendler
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Patent number: 10719326Abstract: In one embodiment, a processor includes: a core to execute instructions, the core including a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages; a first core perimeter logic coupled to the core and including a first storage to store state information of the core when the core is in a low power state; and a second core perimeter logic coupled to the first core perimeter logic and the core, the second core perimeter logic including a second storage to store the state information of the core when the first core perimeter logic is in a low power state. Other embodiments are described and claimed.Type: GrantFiled: February 1, 2018Date of Patent: July 21, 2020Assignee: Intel CorporationInventors: Alexander Gendler, Larisa Novakovsky, Ariel Szapiro
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Publication number: 20200110460Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.Type: ApplicationFiled: July 16, 2019Publication date: April 9, 2020Inventors: Alexander Gendler, Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell
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Patent number: 10365707Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.Type: GrantFiled: December 9, 2016Date of Patent: July 30, 2019Assignee: INTEL CORPORATIONInventors: Alexander Gendler, Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell
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Publication number: 20190101969Abstract: In an embodiment, a processor includes a power control unit, a master processing engine, a set of slave processing engines, and a voltage regulator. The master processing engine is to, in response to a receipt of a change message from the power control unit, control the voltage regulator to adjust a voltage level provided to the master processing engine and the set of slave processing engines. Other embodiments are described and claimed.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Alexander Gendler, Krishnakanth V. Sistla, Ankush Varma, Ariel Szapiro
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Patent number: 10198027Abstract: In one embodiment, a processor includes a credit circuit to communicate credit information between a first clock domain of the processor and a second clock domain of the processor. The credit circuit may include: a loopback path to communicate the credit information between the first clock domain and the second clock domain; and a bypass path to cause the credit information to traverse only a portion of the loopback path, based at least in part on a state of the second clock domain. Other embodiments are described and claimed.Type: GrantFiled: December 6, 2016Date of Patent: February 5, 2019Assignee: Intel CorporationInventors: Alexander Gendler, Ariel Szapiro, Mark Gutman
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Publication number: 20190004583Abstract: Apparatus and methods are provided for improving yield and frequency performance of integrated circuit processors, such as multiple-core processors. In an example, an apparatus can include a plurality of clock buffers, each clock buffer of the plurality of clock buffers configured to receive a first clock signal and distribute a plurality of second clock signals, a one-time programmable locate critical path mechanism configured provide a plurality of indications to enable or disable a delay of each clock buffer of the plurality of clock buffers, and a power management control circuit configured to over-ride one or more of the plurality of indications in a first non-test mode of operation of the apparatus and to not over-ride the one or more indications in a second non-test mode of operation of the apparatus.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Inventors: Yiftach Gilad, Ariel Szapiro, Elkana Korem, Alexander Gendler
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Publication number: 20180181401Abstract: In one embodiment, a processor includes: a core to execute instructions, the core including a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages; a first core perimeter logic coupled to the core and including a first storage to store state information of the core when the core is in a low power state; and a second core perimeter logic coupled to the first core perimeter logic and the core, the second core perimeter logic including a second storage to store the state information of the core when the first core perimeter logic is in a low power state. Other embodiments are described and claimed.Type: ApplicationFiled: February 1, 2018Publication date: June 28, 2018Inventors: Alexander Gendler, Larisa Novakovsky, Ariel Szapiro
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Publication number: 20180164870Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.Type: ApplicationFiled: December 8, 2016Publication date: June 14, 2018Inventors: Alexander Gendler, Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell
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Publication number: 20180164873Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.Type: ApplicationFiled: December 9, 2016Publication date: June 14, 2018Inventors: Alexander Gendler, Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell
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Publication number: 20180157287Abstract: In one embodiment, a processor includes a credit circuit to communicate credit information between a first clock domain of the processor and a second clock domain of the processor. The credit circuit may include: a loopback path to communicate the credit information between the first clock domain and the second clock domain; and a bypass path to cause the credit information to traverse only a portion of the loopback path, based at least in part on a state of the second clock domain. Other embodiments are described and claimed.Type: ApplicationFiled: December 6, 2016Publication date: June 7, 2018Inventors: Alexander Gendler, Ariel Szapiro, Mark Gutman
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Publication number: 20170149554Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.Type: ApplicationFiled: November 24, 2015Publication date: May 25, 2017Applicant: Intel CorporationInventors: Alexander Gendler, Ernest Knoll, Ofer Nathan, Michael Mishaeli, Krishnakanth V. Sistla, Ariel Sabba, Shani Rehana, Ariel Szapiro, Tsvika Kurts, Ofer Levy
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Patent number: 9660799Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.Type: GrantFiled: November 24, 2015Date of Patent: May 23, 2017Assignee: Intel CorporationInventors: Alexander Gendler, Ernest Knoll, Ofer Nathan, Michael Mishaeli, Krishnakanth V. Sistla, Ariel Sabba, Shani Rehana, Ariel Szapiro, Tsvika Kurts, Ofer Levy
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Publication number: 20160224098Abstract: In one embodiment, a processor includes: a core to execute instructions, the core including a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages; a first core perimeter logic coupled to the core and including a first storage to store state information of the core when the core is in a low power state; and a second core perimeter logic coupled to the first core perimeter logic and the core, the second core perimeter logic including a second storage to store the state information of the core when the first core perimeter logic is in a low power state. Other embodiments are described and claimed.Type: ApplicationFiled: January 30, 2015Publication date: August 4, 2016Inventors: ALEXANDER GENDLER, LARISA NOVAKOVSKY, ARIEL SZAPIRO
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Publication number: 20160224090Abstract: In one embodiment, a processor comprises: a core to execute instructions; a fabric interface logic including a first storage to store state information of the core when the core is in a low power state; and an adapter unit including a second storage to store the state information of the core when the fabric interface logic is in a low power state. Other embodiments are described and claimed.Type: ApplicationFiled: January 30, 2015Publication date: August 4, 2016Inventors: ALEXANDER GENDLER, ARIEL SZAPIRO, NIR TELL