Patents by Inventor Ariel Szapiro

Ariel Szapiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10809790
    Abstract: Apparatus and methods are provided for improving yield and frequency performance of integrated circuit processors, such as multiple-core processors. In an example, an apparatus can include a plurality of clock buffers, each clock buffer of the plurality of clock buffers configured to receive a first clock signal and distribute a plurality of second clock signals, a one-time programmable locate critical path mechanism configured provide a plurality of indications to enable or disable a delay of each clock buffer of the plurality of clock buffers, and a power management control circuit configured to over-ride one or more of the plurality of indications in a first non-test mode of operation of the apparatus and to not over-ride the one or more indications in a second non-test mode of operation of the apparatus.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Yiftach Gilad, Ariel Szapiro, Elkana Korem, Alexander Gendler
  • Patent number: 10719326
    Abstract: In one embodiment, a processor includes: a core to execute instructions, the core including a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages; a first core perimeter logic coupled to the core and including a first storage to store state information of the core when the core is in a low power state; and a second core perimeter logic coupled to the first core perimeter logic and the core, the second core perimeter logic including a second storage to store the state information of the core when the first core perimeter logic is in a low power state. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Larisa Novakovsky, Ariel Szapiro
  • Publication number: 20200110460
    Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.
    Type: Application
    Filed: July 16, 2019
    Publication date: April 9, 2020
    Inventors: Alexander Gendler, Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell
  • Patent number: 10365707
    Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: July 30, 2019
    Assignee: INTEL CORPORATION
    Inventors: Alexander Gendler, Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell
  • Publication number: 20190101969
    Abstract: In an embodiment, a processor includes a power control unit, a master processing engine, a set of slave processing engines, and a voltage regulator. The master processing engine is to, in response to a receipt of a change message from the power control unit, control the voltage regulator to adjust a voltage level provided to the master processing engine and the set of slave processing engines. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Alexander Gendler, Krishnakanth V. Sistla, Ankush Varma, Ariel Szapiro
  • Patent number: 10198027
    Abstract: In one embodiment, a processor includes a credit circuit to communicate credit information between a first clock domain of the processor and a second clock domain of the processor. The credit circuit may include: a loopback path to communicate the credit information between the first clock domain and the second clock domain; and a bypass path to cause the credit information to traverse only a portion of the loopback path, based at least in part on a state of the second clock domain. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Ariel Szapiro, Mark Gutman
  • Publication number: 20190004583
    Abstract: Apparatus and methods are provided for improving yield and frequency performance of integrated circuit processors, such as multiple-core processors. In an example, an apparatus can include a plurality of clock buffers, each clock buffer of the plurality of clock buffers configured to receive a first clock signal and distribute a plurality of second clock signals, a one-time programmable locate critical path mechanism configured provide a plurality of indications to enable or disable a delay of each clock buffer of the plurality of clock buffers, and a power management control circuit configured to over-ride one or more of the plurality of indications in a first non-test mode of operation of the apparatus and to not over-ride the one or more indications in a second non-test mode of operation of the apparatus.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Inventors: Yiftach Gilad, Ariel Szapiro, Elkana Korem, Alexander Gendler
  • Publication number: 20180181401
    Abstract: In one embodiment, a processor includes: a core to execute instructions, the core including a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages; a first core perimeter logic coupled to the core and including a first storage to store state information of the core when the core is in a low power state; and a second core perimeter logic coupled to the first core perimeter logic and the core, the second core perimeter logic including a second storage to store the state information of the core when the first core perimeter logic is in a low power state. Other embodiments are described and claimed.
    Type: Application
    Filed: February 1, 2018
    Publication date: June 28, 2018
    Inventors: Alexander Gendler, Larisa Novakovsky, Ariel Szapiro
  • Publication number: 20180164870
    Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.
    Type: Application
    Filed: December 8, 2016
    Publication date: June 14, 2018
    Inventors: Alexander Gendler, Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell
  • Publication number: 20180164873
    Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 14, 2018
    Inventors: Alexander Gendler, Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell
  • Publication number: 20180157287
    Abstract: In one embodiment, a processor includes a credit circuit to communicate credit information between a first clock domain of the processor and a second clock domain of the processor. The credit circuit may include: a loopback path to communicate the credit information between the first clock domain and the second clock domain; and a bypass path to cause the credit information to traverse only a portion of the loopback path, based at least in part on a state of the second clock domain. Other embodiments are described and claimed.
    Type: Application
    Filed: December 6, 2016
    Publication date: June 7, 2018
    Inventors: Alexander Gendler, Ariel Szapiro, Mark Gutman
  • Publication number: 20170149554
    Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.
    Type: Application
    Filed: November 24, 2015
    Publication date: May 25, 2017
    Applicant: Intel Corporation
    Inventors: Alexander Gendler, Ernest Knoll, Ofer Nathan, Michael Mishaeli, Krishnakanth V. Sistla, Ariel Sabba, Shani Rehana, Ariel Szapiro, Tsvika Kurts, Ofer Levy
  • Patent number: 9660799
    Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Ernest Knoll, Ofer Nathan, Michael Mishaeli, Krishnakanth V. Sistla, Ariel Sabba, Shani Rehana, Ariel Szapiro, Tsvika Kurts, Ofer Levy
  • Publication number: 20160224090
    Abstract: In one embodiment, a processor comprises: a core to execute instructions; a fabric interface logic including a first storage to store state information of the core when the core is in a low power state; and an adapter unit including a second storage to store the state information of the core when the fabric interface logic is in a low power state. Other embodiments are described and claimed.
    Type: Application
    Filed: January 30, 2015
    Publication date: August 4, 2016
    Inventors: ALEXANDER GENDLER, ARIEL SZAPIRO, NIR TELL
  • Publication number: 20160224098
    Abstract: In one embodiment, a processor includes: a core to execute instructions, the core including a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages; a first core perimeter logic coupled to the core and including a first storage to store state information of the core when the core is in a low power state; and a second core perimeter logic coupled to the first core perimeter logic and the core, the second core perimeter logic including a second storage to store the state information of the core when the first core perimeter logic is in a low power state. Other embodiments are described and claimed.
    Type: Application
    Filed: January 30, 2015
    Publication date: August 4, 2016
    Inventors: ALEXANDER GENDLER, LARISA NOVAKOVSKY, ARIEL SZAPIRO
  • Patent number: 9292927
    Abstract: Systems, apparatus and methods are described related to adaptive support windows for stereoscopic image correlation.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Dror Reif, Ariel Szapiro
  • Patent number: 9104542
    Abstract: A method is described that includes reading a cache tag and the cache tag's corresponding ECC from storage circuitry of a cache. The method also includes generating an ECC for a search tag. The method also includes calculating a hamming distance between a) the cache tag and its corresponding ECC and b) the search tag and its corresponding ECC. The method also includes determining if the cache tag matches the search tag by determining if said hamming distance is two or less.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: August 11, 2015
    Assignee: Intel Corporation
    Inventors: Ariel Szapiro, Alexander Gendler
  • Publication number: 20140189473
    Abstract: A method is described that includes reading a cache tag and the cache tag's corresponding ECC from storage circuitry of a cache. The method also includes generating an ECC for a search tag. The method also includes calculating a hamming distance between a) the cache tag and its corresponding ECC and b) the search tag and its corresponding ECC. The method also includes determining if the cache tag matches the search tag by determining if said hamming distance is two or less.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Ariel SZAPIRO, Alexander GENDLER
  • Publication number: 20140184584
    Abstract: Systems, apparatus and methods are described related to adaptive support windows for stereoscopic image correlation.
    Type: Application
    Filed: December 27, 2012
    Publication date: July 3, 2014
    Inventors: Dror Reif, Ariel Szapiro
  • Patent number: 8707131
    Abstract: A method is described that includes reading a cache tag and the cache tag's corresponding ECC from storage circuitry of a cache. The method also includes generating an ECC for a search tag. The method also includes calculating a hamming distance between a) the cache tag and its corresponding ECC and b) the search tag and its corresponding ECC. The method also includes determining if the cache tag matches the search tag by comparing the hamming distance against a threshold.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: April 22, 2014
    Assignee: Intel Corporation
    Inventors: Ariel Szapiro, Alexander Gendler, Eugene Gorkov