Abstract: Various embodiments provide semiconductor devices including high-K dielectric layer(s) and fabrication methods. An exemplary high-K dielectric layer can be formed by providing a semiconductor substrate including a first region and a second region, and forming a first silicon oxide layer on the semiconductor substrate in the first region. The semiconductor substrate can then be placed in an atomic layer deposition (ALD) chamber to repeatedly perform a selective ALD process. The selective ALD process can include an etching process and/or a purging process in the ALD chamber. By repeatedly performing the selective ALD process, a first high-K dielectric layer can be selectively formed on the first silicon oxide layer in the first region, exposing the semiconductor substrate in the second region.

Abstract: An SOI substrate and a method for forming the SOI substrate are provided. An SOI substrate can be formed by forming a silicon-germanium layer on a first baseplate. A top silicon layer can be formed on the silicon-germanium layer. A first insulating layer can be formed on the top silicon layer. An ion implanted layer can be formed in one of the silicon-germanium layer and the first baseplate. A second baseplate can be bonded to the first insulating layer. A first annealing process can be performed to anneal and split the one of the silicon-germanium layer and the first baseplate at the ion implanted layer. The silicon-germanium layer can be removed from the top silicon layer to expose the top silicon layer and to form the SOI substrate comprising the first insulating layer formed between the top silicon layer and the second baseplate.

Abstract: Various embodiments provide semiconductor devices including high-K dielectric layer(s) and fabrication methods. An exemplary high-K dielectric layer can be formed by providing a semiconductor substrate including a first region and a second region, and forming a first silicon oxide layer on the semiconductor substrate in the first region. The semiconductor substrate can then be placed in an atomic layer deposition (ALD) chamber to repeatedly perform a selective ALD process. The selective ALD process can include an etching process and/or a purging process in the ALD chamber. By repeatedly performing the selective ALD process, a first high-K dielectric layer can be selectively formed on the first silicon oxide layer in the first region, exposing the semiconductor substrate in the second region.

Abstract: A fast installation/removal structure includes an upper board, a lower board, and an installation/removal lever. The upper board has hooking grooves and at least a positioning pin. The lower board has snap fitting devices and at least a sliding slot through which slidably inserts the positioning pin. A front end of the lever is pivotally connected to the lower board there below, and has a guide groove through which the positioning pin inserts. A rear end of the lever is externally accessible to allow manipulation by the user. With the circuit board securely fastened thereon, the upper board is placed on the lower board. The snap fitting devices respectively engage through the hooking grooves. By turning the lever, the positioning pin slides along the sliding slot to have the snap fitting devices respectively snap fit through the hooking grooves, thereby fastening the upper board to the lower board.

Abstract: A fast installation/removal structure includes an upper board, a lower board, and an installation/removal lever. The upper board has hooking grooves and at least a positioning pin. The lower board has snap fitting devices and at least a sliding slot through which slidably inserts the positioning pin. A front end of the lever is pivotally connected to the lower board there below, and has a guide groove through which the positioning pin inserts. A rear end of the lever is externally accessible to allow manipulation by the user. With the circuit board securely fastened thereon, the upper board is placed on the lower board. The snap fitting devices respectively engage through the hooking grooves. By turning the lever, the positioning pin slides along the sliding slot to have the snap fitting devices respectively snap fit through the hooking grooves, thereby fastening the upper board to the lower board.

Abstract: A fixing structure for extension cards includes a set of extension slots, a positioning element and a resilient plate. The positioning element engages on an external side of the set of the extension slots, and the resilient plate is fixing on an internal side of the set of the extension slots. A folded edge of the resilient plate is inserted through a first mounting slot of the positioning element to firmly secure the positioning element on a computer casing. A stem of the resilient plate is pulled toward an inside of the computer casing to release the folded edge of the resilient plate from the first mounting slot of the positioning element so that the positioning element is pushed upward to disengage from the set of extension slots.