Patents by Inventor Arifur Rahman

Arifur Rahman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11870527
    Abstract: A radio access network operates by obtaining, at a scheduler, CSI corresponding to a plurality of RUs associated with a master DU and another plurality of RUs associated with at least one other DU, wherein the CSI associated with the another plurality of RUs is obtained via another scheduler or via the at least one other DU; allocating, based on the CSI, a resource allocation for resource blocks associated with the plurality of RUs and the another plurality of RUs; negotiating with the another scheduler to obtain PRB resources of RUs controlled by the another scheduler; generating, based on the CSI, precoders associated with the plurality of RUs and the another plurality of RUs; and facilitating, via the master DU and based on the precoders and the resource allocation, contemporaneous transmission to a user equipment UE via the plurality of RUs and the another plurality of RUs and contemporaneous reception from the user equipment UE via the plurality of RUs and the another plurality of RUs.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: January 9, 2024
    Assignees: ISRD Sp. z o.o., ISN Sp. z o.o.
    Inventors: Adam Girycki, Md Arifur Rahman, Michal Piotr Pajak, Jakub Piotr Kocot, Adam Dawid Flizikowski, Slawomir Pietrzyk
  • Patent number: 11857005
    Abstract: A fully adjustable hybrid personal cooling and heating system is configured to remove or supply heat from/to a human user. The system is specifically designed to provide up to 8-hours of high efficiency adjustable cooling or heating when worn and operated by a user. The personal cooling and heating system use non-toxic room-temperature liquid metal as primary coolant and phase-change material as secondary coolant. The primary coolant is pumped using an active powered pump which absorbs heat from the user's body, and passively release the heat to the secondary coolant making the invention a hybrid cooling/heating system. Passive heat release is facilitated by extreme high thermal conductivity of the primary coolant. Also, the secondary coolant is thermally insulated from the environment allowing on-demand heat absorption only from the primary coolant.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: January 2, 2024
    Inventor: M Arifur Rahman
  • Publication number: 20230409515
    Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.
    Type: Application
    Filed: August 28, 2023
    Publication date: December 21, 2023
    Inventors: Chee Hak Teh, Arifur Rahman
  • Publication number: 20230394235
    Abstract: Systems and methods are described for automatically inspecting and validating unstructured documents having natural language text, such as journal article describing clinical research. For example, a journal's prose may be parsed to identify domain-specific entities and values. Domain-specific rules may be evaluated against generated structured data storing the entities and their corresponding values. rule may relate to a domain-specific requirement for the document. Findings may be generated for each evaluated rule, indicating whether the document meets a corresponding requirement. Feedback indicating whether a given finding is incorrect or is to be updated, which may indicate that the corresponding rule should be updated or removed, may be obtained. Based on the feedback, the set of domain-specific rules may be updated to obtain an updated set of rules including an update to or deletion of the rule. Some embodiments include automatically validating documents using voice enabled features.
    Type: Application
    Filed: June 6, 2023
    Publication date: December 7, 2023
    Applicant: Otsuka Pharmaceutical Development & Commercialization, Inc.
    Inventors: Mohammed Arifur RAHMAN, Nityanand CHOUBEY, Imtiaz MOHIUDDIN, Paresh PATEL, Babu Sudhagar RAJ, Mehul SHAH
  • Patent number: 11832644
    Abstract: A process for producing a filter element suitable for use in smoking articles may include: embedding a bundle of cellulose acetate fibers with an aqueous suspension of polyhydroxyalkanoate (PHA) to obtain a wet bundle of the cellulose acetate fibers covered by the aqueous suspension of the PHA; shaping the wet bundle in a form of a continuous elongated element; heating the continuous elongated element to temperature greater than or equal to 140° C. and less than or equal to 180° C. for time sufficient to melt the PHA and to evaporate water from the continuous elongated element; cooling the heated continuous elongated element to obtain crystallization of the PHA; and cutting the so-obtained continuous elongated element into segments of predetermined length.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: December 5, 2023
    Assignee: BIO-ON S.p.A.
    Inventors: Paolo Saettone, Ilaria Monaco, Thomas M. Holsen, Mohammad Arifur Rahman, Philip K. Hopke, Mauro Comes Franchini
  • Patent number: 11741042
    Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.
    Type: Grant
    Filed: December 24, 2021
    Date of Patent: August 29, 2023
    Assignee: Altera Corporation
    Inventors: Chee Hak Teh, Arifur Rahman
  • Patent number: 11726132
    Abstract: A failure detection system for an energy network includes a radio frequency (RF) receiver adapted to be coupled with or in close proximity to the energy network, the RF receiver providing an amplitude modulated RF signal; an RF amplifier receiving the amplitude modulated RF signal and providing an amplified signal; an envelope detector receiving the amplitude modulated RF signal and providing a demodulated envelope signal; an optional algorithm implementation system receiving the demodulated envelope signal, where the optional algorithm implementation system processes the demodulated envelope signal by one or more of a Fast Fourier transform (FFT) trigger system and a phase-locked loop (PLL) trigger system; and a signature output that is the overall output signal of the failure detection system, wherein the signature output is adapted to indicate whether the energy network is experiencing partial discharge.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: August 15, 2023
    Assignee: The University of Akron
    Inventors: Yilmaz Sozer, Jose Alexis De Abreu-Garcia, Mohammad Arifur Rahman
  • Publication number: 20230239027
    Abstract: A radio access network operates by obtaining, at a scheduler, CSI corresponding to a plurality of RUs associated with a master DU and another plurality of RUs associated with at least one other DU, wherein the CSI associated with the another plurality of RUs is obtained via another scheduler or via the at least one other DU; allocating, based on the CSI, a resource allocation for resource blocks associated with the plurality of RUs and the another plurality of RUs; negotiating with the another scheduler to obtain PRB resources of RUs controlled by the another scheduler; generating, based on the CSI, precoders associated with the plurality of RUs and the another plurality of RUs; and facilitating, via the master DU and based on the precoders and the resource allocation, contemporaneous transmission to a user equipment UE via the plurality of RUs and the another plurality of RUs and contemporaneous reception from the user equipment UE via the plurality of RUs and the another plurality of RUs.
    Type: Application
    Filed: January 19, 2023
    Publication date: July 27, 2023
    Applicants: ISRD Sp. z o.o., ISN Sp. z o.o.
    Inventors: Adam Girycki, Md Arifur Rahman, Michal Piotr Pajak, Jakub Piotr Kocot, Adam Dawid Flizikowski, Slawomir Pietrzyk
  • Patent number: 11500674
    Abstract: A system for running one or more applications is provided. Each application may require memory services that can be accelerated using configurable memory assistance circuits associated with different levels of a memory hierarchy. Integrated circuit design tools may be used to generate configuration data for programming the configurable memory assistance circuits. During compile time, the design tools may identify memory service patterns in a source code, match the identified memory service patterns to corresponding templates, parameterize the matching templates, and then synthesize the parameterized templates to produce the configuration data. During run time, a memory assistance scheduler may map the memory services required by each application to available memory assistance circuits in the system. The mapped memory assistance circuits are programmed by the configuration data to provide the desired memory service capability.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: November 15, 2022
    Assignee: Intel Corporation
    Inventors: Robert L. Pelt, Hong Wang, Arifur Rahman
  • Patent number: 11502793
    Abstract: A cooperative radio resource manager operates by: obtaining constraint data indicating a plurality of radio network constraints and channel state information (CSI) corresponding to wireless communications between a plurality of client devices and a plurality of remote radio heads; performing a first sub-problem optimization, subject to the plurality of radio network constraints, to generate an remote radio head (RRH) to client device association that associates a corresponding one of the plurality of remote radio heads to each of the plurality of client devices and further to generate a physical resource block (PRB) allocation that allocates PRBs of each RRH among the plurality of client devices.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: November 15, 2022
    Assignee: ISRD Sp. z o.o.
    Inventors: Md Arifur Rahman, Farinaz Kooshki, Suvidha Mhatre, Slawomir Pietrzyk, Adam Flizikowski
  • Patent number: 11487445
    Abstract: A system may include a host processor, a coprocessor for accelerating tasks received from the host processor, and one or more memory dies mounted to the coprocessor. The coprocessor and the memory die may be part of an integrated circuit package. The memory die may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor over through-silicon vias. Each logic sector may include one or more data registers that are loaded with configuration data from the memory die. Multiple data registers may be loaded with configuration data simultaneously. The configuration data may be loaded onto an array of configuration memory cells using the data registers. Multiple data registers may be pipelined to allow simultaneous loading of configuration data into multiple sub-arrays of the array of configuration memory cells.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: November 1, 2022
    Assignee: Intel Corporation
    Inventors: Aravind Dasu, Scott Weber, Jun Pin Tan, Arifur Rahman
  • Publication number: 20220322737
    Abstract: A process for producing a filter element suitable for use in smoking articles may include: embedding a bundle of cellulose acetate fibers with an aqueous suspension of polyhydroxyalkanoate (PHA) to obtain a wet bundle of the cellulose acetate fibers covered by the aqueous suspension of the PHA; shaping the wet bundle in a form of a continuous elongated element; heating the continuous elongated element to temperature greater than or equal to 140° C. and less than or equal to 180° C. for time sufficient to melt the PHA and to evaporate water from the continuous elongated element; cooling the heated continuous elongated element to obtain crystallization of the PHA; and cutting the so-obtained continuous elongated element into segments of predetermined length.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 13, 2022
    Inventors: Paolo SAETTONE, Ilaria MONACO, Thomas M. HOLSEN, Mohammad Arifur RAHMAN, Philip K. HOPKE, Mauro COMES FRANCHINI
  • Patent number: 11422954
    Abstract: A computer system includes a processor circuit, first and second memory systems, and a configurable memory assistance circuit. The processor circuit is used to run at least one application. The application issues a memory access operation. The configurable memory assistance circuit is in communication with the first and second memory systems and the processor circuit. The configurable memory assistance circuit accelerates the memory access operation for the application using data as the data is in transit between the first and second memory systems.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 23, 2022
    Assignee: Intel Corporation
    Inventors: Robert Pelt, Arifur Rahman, Hong Wang
  • Publication number: 20220214982
    Abstract: Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Inventors: Arifur Rahman, Bernhard Friebe
  • Publication number: 20220173849
    Abstract: A cooperative radio resource manager operates by: obtaining constraint data indicating a plurality of radio network constraints and channel state information (CSI) corresponding to wireless communications between a plurality of client devices and a plurality of remote radio heads; performing a first sub-problem optimization, subject to the plurality of radio network constraints, to generate an remote radio head (RRH) to client device association that associates a corresponding one of the plurality of remote radio heads to each of the plurality of client devices and further to generate a physical resource block (PRB) allocation that allocates PRBs of each RRH among the plurality of client devices.
    Type: Application
    Filed: November 23, 2021
    Publication date: June 2, 2022
    Applicants: ISN Sp. z o.o., ISRD Sp. z o.o.
    Inventors: Md Arifur Rahman, Farinaz Kooshki, Suvidha Mhatre, Slawomir Pietrzyk, Adam Flizikowski
  • Publication number: 20220121616
    Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2x clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.
    Type: Application
    Filed: December 24, 2021
    Publication date: April 21, 2022
    Inventors: Chee Hak Teh, Arifur Rahman
  • Patent number: 11281605
    Abstract: Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: March 22, 2022
    Assignee: Altera Corporation
    Inventors: Arifur Rahman, Bernhard Friebe
  • Patent number: 11226925
    Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: January 18, 2022
    Assignee: Altera Corporation
    Inventors: Chee Hak Teh, Arifur Rahman
  • Patent number: 11194757
    Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: December 7, 2021
    Assignee: Altera Corporation
    Inventors: Chee Hak Teh, Arifur Rahman
  • Publication number: 20210373066
    Abstract: A failure detection system for an energy network includes a radio frequency (RF) receiver adapted to be coupled with or in close proximity to the energy network, the RF receiver providing an amplitude modulated RF signal; an RF amplifier receiving the amplitude modulated RF signal and providing an amplified signal; an envelope detector receiving the amplitude modulated RF signal and providing a demodulated envelope signal; an optional algorithm implementation system receiving the demodulated envelope signal, where the optional algorithm implementation system processes the demodulated envelope signal by one or more of a Fast Fourier transform (FFT) trigger system and a phase-locked loop (PLL) trigger system; and a signature output that is the overall output signal of the failure detection system, wherein the signature output is adapted to indicate whether the energy network is experiencing partial discharge.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 2, 2021
    Inventors: Yilmaz Sozer, Jose Alexis De Abreu-Garcia, Mohammad Arifur Rahman