Abstract: A generator-rectifier system and grid interface includes an active rectifier configured to accept an input from one of a plurality of ac ports of a multi-port permanent magnet synchronous generator. Passive rectifiers are connected to the others of the plurality of ac ports. Connections provide outputs of the active rectifier and the passive rectifiers. A first converter is controlled at a fixed duty ratio driven by the outputs to interface with a dc grid or at a low grid frequency switching waveform to create a grid frequency ac output to interface with an ac grid. A second converter is connected the output of the active rectifier, the second converter being controlled at a variable duty ratio to interface with the dc grid or an above grid frequency switching waveform to create an above grid frequency ac waveform to interface with an ac grid. Connections provide a serial stack of outputs of the first and second converters.

Abstract: The disclosed embodiments provide a method for interconnecting a plurality of networks, including a first network, with a second network via an interworking gateway (IWG). The method may comprise receiving a request from the first network for a user in the first network to access at least one service or application available in the second network, determining at least one criteria associated with the second network to enforce for the user in the first network, and enforcing the at least one criteria for communications associated with the user between the first and second networks. The IWG may be a cloud-based service that is configured to perform the aforementioned steps. The IWG may also be configured to be dynamically scalable to support multiple networks in the plurality of networks requesting interconnection with the second network.

Abstract: An integrated multi-port generator-rectifier device includes multiple passive output ports provided from a plurality of passive-rectifier windings on a common, single magnetic structure. The passive-rectifier windings interact with a plurality of magnetic poles. Coils in the passive rectifier windings are serially connected. Each of the passive rectifier windings has a pitch as that is a fraction of magnet pole pitch and a pattern to magnetically decouple back emf phases of the separate rectifiers. The device further includes an active port provided by an active rectifier.

Abstract: Methods and systems for providing multipath connectivity intelligence is disclosed. The system may include one or more processors; and a memory storing instructions that cause the one or more processors to perform the steps comprising: connecting, by an intelligence interface, an agent to an intelligence service, transmitting, by the intelligence interface, information associated with the agent to the intelligence service, and receiving, by the intelligence interface, one or more connectivity options associated with the agent from the intelligence service. The agent may be a logical entity comprising one or more functions configured to manage multipath connectivity, and the one or more connectivity options may be used by one or more networks or one or more device functions for multipath management and scheduling.

Abstract: The disclosed embodiments provide a method for interconnecting a plurality of networks, including a first network, with a second network via an interworking gateway (IWG). The method may comprise receiving a request from the first network for a user in the first network to access at least one service or application available in the second network, determining at least one criteria associated with the second network to enforce for the user in the first network, and enforcing the at least one criteria for communications associated with the user between the first and second networks. The IWG may be a cloud-based service that is configured to perform the aforementioned steps. The IWG may also be configured to be dynamically scalable to support multiple networks in the plurality of networks requesting interconnection with the second network.

Abstract: Example embodiments relate generally to systems and methods for continuous data protection (CDP) and more specifically to an input and output (I/O) filtering framework and log management system to seek a near-zero recovery point objective (RPO).

Abstract: Example embodiments relate generally to systems and methods for continuous data protection (CDP) and more specifically to an input and output (I/O) filtering framework and log management system to seek a near-zero recovery point objective (RPO).

Abstract: Example embodiments relate generally to systems and methods for continuous data protection (CDP) and more specifically to an input and output (I/O) filtering framework and log management system to seek a near-zero recovery point objective (RPO).

Abstract: Example embodiments relate generally to systems and methods for continuous data protection (CDP) and more specifically to an input and output (I/O) filtering framework and log management system to seek a near-zero recovery point objective (RPO).

Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. Adjacent bit cells in a column of an array use a split read port such that the bit cells do not share a read bit line while sharing a write bit line. The adjacent bit cells include asymmetrical read access circuits that convey data stored by latch circuitry of a corresponding bit cell to a corresponding read bit line. The layout of adjacent bit cells provides a number of contacted gate pitches per bit cell that is less than a sum of the maximum number of metal gates in layout of each of the adjacent bit cells divided by the number of adjacent bit cells.

Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. A dual read port and single write port memory bit cell uses two asymmetrical read access circuits for conveying stored data on two read bit lines. The two read bit lines are pre-charged to different voltage reference levels. The layout of the memory bit cell places the two read bit lines on an opposed edge from the single write bit line. The layout uses a dummy gate placed over both p-type diffusion and n-type diffusion between the edges. The layout has a same number of p-type transistors as n-type transistors despite using asymmetrical read access circuits. The layout also has a contacted gate pitch that is one more than the number of p-type transistors.

Abstract: Example embodiments relate generally to systems and methods for continuous data protection (CDP) and more specifically to an input and output (I/O) filtering framework and log management system to seek a near-zero recovery point objective (RPO).

Abstract: An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.

Abstract: Embodiments provide an access point (AP) that includes a set of one or more base-station functions configured to connect a user equipment (UE) to the AP over a wireless communication interface; and a set of one or more core-network functions configured to provide services to the UE. The AP allocates an Internet Protocol (IP) address to the UE by using at least one Dynamic Host Configuration Protocol (DHCP) server that is external to the AP.

Abstract: A read path for reading data from a memory includes a sense amplifier having data (SAT) and data complement (SAC) output nodes and a latch. The latch includes an input tri-state inverter including first and second PMOS transistors connected between VDD and an intermediate node, and first and second NMOS transistors connected between VSS and the intermediate node. A gate connection of the first PMOS and NMOS transistors is connected to the SAT node; a gate connection of the second PMOS transistor is connected to a sense amplifier enable complement input; and a gate connection of the second NMOS transistor is connected to a sense amplifier enable input. The latch also includes an output driver with an input connected to the intermediate node and an output connected to a data output node. The latch thus has two gate delays between the SAT node and the data output node.

Abstract: An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.

Abstract: This disclosure relates AC-to-DC rectification and power flow control of electrical power generators. An integrated rectifier-generator AC-DC conversion circuit and system are disclosed for providing a regulated DC output. The integrated rectifier-generator AC-DC conversion circuit and system may include serially stacked passive and active rectifiers connected to multiple AC ports of an electrical power generator driven by mechanical energy captured by an energy harvester. The integrated rectifier-generator AC-DC conversion circuit and system may be configured to perform active ripple control and a maximum power tracking from the energy harvester by controlling a fraction of an overall power that flow through the active rectifier.

Abstract: In some examples, a method of continuous data protection for a virtual machine (VM) having a virtual disk is provided. An example method comprises implementing a recovery protocol for the VM, the recovery protocol including a recovery point objective (RPO) of less than a threshold time period, obtaining a base snapshot of the virtual disk. The method includes intercepting, at an interception point in an I/O path, a virtual disk I/O stream and replicating the I/O stream at a log receiver, storing the replicated I/O stream in I/O logs, and forming a recoverable snapshot-log chain by applying the replicated I/O stream stored in the I/O logs to the base snapshot. A user request is received for recoverable data at a replication target, the request being covered by the RPO, the method further including meeting or exceeding the RPO by sending data to the replication target based at least on a portion of the recoverable snapshot-log chain.

Abstract: Example embodiments relate generally to systems and methods for continuous data protection (CDP) and more specifically to an input and output (I/O) filtering framework and log management system to seek a near-zero recovery point objective (RPO).

Abstract: Example embodiments relate generally to systems and methods for continuous data protection (CDP) and more specifically to an input and output (I/O) filtering framework and log management system to seek a near-zero recovery point objective (RPO).