Patents by Inventor Arik Rizel

Arik Rizel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9672925
    Abstract: A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: June 6, 2017
    Assignee: Apple Inc.
    Inventors: Arik Rizel, Avraham Poza Meir, Yael Shur, Eyal Gurgi, Barak Baum
  • Publication number: 20160189783
    Abstract: A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.
    Type: Application
    Filed: March 10, 2016
    Publication date: June 30, 2016
    Inventors: Arik Rizel, Avraham Poza Meir, Yael Shur, Eyal Gurgi, Barak Baum
  • Patent number: 9312017
    Abstract: A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: April 12, 2016
    Assignee: Apple Inc.
    Inventors: Arik Rizel, Avraham Poza Meir, Yael Shur, Eyal Gurgi, Barak Baum
  • Publication number: 20150200016
    Abstract: A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.
    Type: Application
    Filed: August 12, 2014
    Publication date: July 16, 2015
    Inventors: Arik Rizel, Avraham Poza Meir, Yael Shur, Eyal Gurgi, Barak Baum
  • Patent number: 7742339
    Abstract: Selecting a read voltage level for a NVM cell by using an initial value for the read voltage and performing a read operation, comparing an actual number of bits found to an expected number of bits and, if there is a discrepancy between the actual number and the expected number, adjusting the read voltage level, based on variable data such as statistics available, level occupation, neighbor level, previous chunks data, and other data used during read, program or erase. For example, based on a number of missing bits, or upon a result of a previous read operation, or a result obtained at another program level, or upon how many times the memory cell has been cycled, or upon how many memory cells are at each program level, or on a number of bits at another program level in a selected chunk of memory.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: June 22, 2010
    Assignee: Saifun Semiconductors Ltd.
    Inventors: Arik Rizel, Guy Cohen
  • Publication number: 20090003073
    Abstract: Selecting a read voltage level for a NVM cell by using an initial value for the read voltage and performing a read operation, comparing an actual number of bits found to an expected number of bits and, if there is a discrepancy between the actual number and the expected number, adjusting the read voltage level, based on variable data such as statistics available, level occupation, neighbor level, previous chunks data, and other data used during read, program or erase. For example, based on a number of missing bits, or upon a result of a previous read operation, or a result obtained at another program level, or upon how many times the memory cell has been cycled, or upon how many memory cells are at each program level, or on a number of bits at another program level in a selected chunk of memory.
    Type: Application
    Filed: January 10, 2007
    Publication date: January 1, 2009
    Inventors: Arik Rizel, Guy Cohen