Patents by Inventor Arik Zafrany

Arik Zafrany has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11139779
    Abstract: A dual-band mixer circuit includes a mixer configured to receive an input signal and a local oscillator (LO) signal and to generate an output frequency signal, and a switchable inductance circuit coupled to an output of the mixer, and including a transformer including a primary inductor and a secondary inductor, the primary inductor being electrically coupled to the output of the mixer, a capacitor electrically coupled to the secondary inductor, and a switch electrically coupled to the capacitor and the secondary inductor.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: October 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Arik Zafrany
  • Publication number: 20210119580
    Abstract: A dual-band mixer circuit includes a mixer configured to receive an input signal and a local oscillator (LO) signal and to generate an output frequency signal, and a switchable inductance circuit coupled to an output of the mixer, and including a transformer including a primary inductor and a secondary inductor, the primary inductor being electrically coupled to the output of the mixer, a capacitor electrically coupled to the secondary inductor, and a switch electrically coupled to the capacitor and the secondary inductor.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 22, 2021
    Inventor: Arik Zafrany
  • Patent number: 9673815
    Abstract: A circuit may include first and second input nodes, first and second output nodes, first and second intermediate nodes, first and second resistances, a first amplification transistor coupled to the first input node, the first resistance, and the first intermediate node and a second amplification transistor coupled to the second input node, the second resistance, and the second intermediate node. The circuit may also include a first active device coupled to the first output node and the first intermediate node, a second active device coupled to the second output node and the second intermediate node, a first output transistor coupled to the first output node and configured to conduct based on a second intermediate signal on the second intermediate node, and a second output transistor coupled to the second output node and configured to conduct based on a first intermediate signal on the first intermediate node.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: June 6, 2017
    Assignee: FINISAR CORPORATION
    Inventors: Arik Zafrany, Georgios Kalogerakis
  • Publication number: 20170033795
    Abstract: A circuit may include first and second input nodes, first and second output nodes, first and second intermediate nodes, first and second resistances, a first amplification transistor coupled to the first input node, the first resistance, and the first intermediate node and a second amplification transistor coupled to the second input node, the second resistance, and the second intermediate node. The circuit may also include a first active device coupled to the first output node and the first intermediate node, a second active device coupled to the second output node and the second intermediate node, a first output transistor coupled to the first output node and configured to conduct based on a second intermediate signal on the second intermediate node, and a second output transistor coupled to the second output node and configured to conduct based on a first intermediate signal on the first intermediate node.
    Type: Application
    Filed: August 1, 2016
    Publication date: February 2, 2017
    Inventors: Arik ZAFRANY, Georgios KALOGERAKIS
  • Patent number: 9407259
    Abstract: A circuit may include first and second input nodes, first and second output nodes, first and second intermediate nodes, first and second resistances, a first amplification transistor coupled to the first input node, the first resistance, and the first intermediate node and a second amplification transistor coupled to the second input node, the second resistance, and the second intermediate node. The circuit may also include a first active device coupled to the first output node and the first intermediate node, a second active device coupled to the second output node and the second intermediate node, a first output transistor coupled to the first output node and configured to conduct based on a second intermediate signal on the second intermediate node, and a second output transistor coupled to the second output node and configured to conduct based on a first intermediate signal on the first intermediate node.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: August 2, 2016
    Assignee: FINISAR CORPORATION
    Inventors: Arik Zafrany, Georgios Kalogerakis
  • Publication number: 20150381172
    Abstract: A circuit may include first and second input nodes, first and second output nodes, first and second intermediate nodes, first and second resistances, a first amplification transistor coupled to the first input node, the first resistance, and the first intermediate node and a second amplification transistor coupled to the second input node, the second resistance, and the second intermediate node. The circuit may also include a first active device coupled to the first output node and the first intermediate node, a second active device coupled to the second output node and the second intermediate node, a first output transistor coupled to the first output node and configured to conduct based on a second intermediate signal on the second intermediate node, and a second output transistor coupled to the second output node and configured to conduct based on a first intermediate signal on the first intermediate node.
    Type: Application
    Filed: June 27, 2014
    Publication date: December 31, 2015
    Inventors: Arik ZAFRANY, Georgios KALOGERAKIS
  • Patent number: 9148129
    Abstract: A circuit may include an input node configured to receive a signal and an output node configured to be coupled to a load. The circuit may also include a first circuit coupled between the input node and the output node, the first circuit being configured to receive the signal and drive the signal on the output node at a first voltage. The circuit may also include a signal adjust circuit configured to adjust a current of the signal driven by the first circuit. The signal adjust circuit may be configured to apply a first current adjustment to adjust the current of the signal at one but not both of a falling edge of the signal or a rising edge of the signal.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: September 29, 2015
    Assignee: FINISAR CORPORATION
    Inventors: Jason Miao, Arik Zafrany, Georgios Kalogerakis
  • Publication number: 20140361813
    Abstract: A circuit may include an input node configured to receive a signal and an output node configured to be coupled to a load. The circuit may also include a first circuit coupled between the input node and the output node, the first circuit being configured to receive the signal and drive the signal on the output node at a first voltage. The circuit may also include a signal adjust circuit configured to adjust a current of the signal driven by the first circuit. The signal adjust circuit may be configured to apply a first current adjustment to adjust the current of the signal at one but not both of a falling edge of the signal or a rising edge of the signal.
    Type: Application
    Filed: June 7, 2013
    Publication date: December 11, 2014
    Inventors: Jason Miao, Arik Zafrany, Georgios Kalogerakis