Patents by Inventor Arik Zafrany
Arik Zafrany has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11139779Abstract: A dual-band mixer circuit includes a mixer configured to receive an input signal and a local oscillator (LO) signal and to generate an output frequency signal, and a switchable inductance circuit coupled to an output of the mixer, and including a transformer including a primary inductor and a secondary inductor, the primary inductor being electrically coupled to the output of the mixer, a capacitor electrically coupled to the secondary inductor, and a switch electrically coupled to the capacitor and the secondary inductor.Type: GrantFiled: December 5, 2019Date of Patent: October 5, 2021Assignee: Samsung Electronics Co., Ltd.Inventor: Arik Zafrany
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Publication number: 20210119580Abstract: A dual-band mixer circuit includes a mixer configured to receive an input signal and a local oscillator (LO) signal and to generate an output frequency signal, and a switchable inductance circuit coupled to an output of the mixer, and including a transformer including a primary inductor and a secondary inductor, the primary inductor being electrically coupled to the output of the mixer, a capacitor electrically coupled to the secondary inductor, and a switch electrically coupled to the capacitor and the secondary inductor.Type: ApplicationFiled: December 5, 2019Publication date: April 22, 2021Inventor: Arik Zafrany
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Patent number: 9673815Abstract: A circuit may include first and second input nodes, first and second output nodes, first and second intermediate nodes, first and second resistances, a first amplification transistor coupled to the first input node, the first resistance, and the first intermediate node and a second amplification transistor coupled to the second input node, the second resistance, and the second intermediate node. The circuit may also include a first active device coupled to the first output node and the first intermediate node, a second active device coupled to the second output node and the second intermediate node, a first output transistor coupled to the first output node and configured to conduct based on a second intermediate signal on the second intermediate node, and a second output transistor coupled to the second output node and configured to conduct based on a first intermediate signal on the first intermediate node.Type: GrantFiled: August 1, 2016Date of Patent: June 6, 2017Assignee: FINISAR CORPORATIONInventors: Arik Zafrany, Georgios Kalogerakis
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Publication number: 20170033795Abstract: A circuit may include first and second input nodes, first and second output nodes, first and second intermediate nodes, first and second resistances, a first amplification transistor coupled to the first input node, the first resistance, and the first intermediate node and a second amplification transistor coupled to the second input node, the second resistance, and the second intermediate node. The circuit may also include a first active device coupled to the first output node and the first intermediate node, a second active device coupled to the second output node and the second intermediate node, a first output transistor coupled to the first output node and configured to conduct based on a second intermediate signal on the second intermediate node, and a second output transistor coupled to the second output node and configured to conduct based on a first intermediate signal on the first intermediate node.Type: ApplicationFiled: August 1, 2016Publication date: February 2, 2017Inventors: Arik ZAFRANY, Georgios KALOGERAKIS
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Patent number: 9407259Abstract: A circuit may include first and second input nodes, first and second output nodes, first and second intermediate nodes, first and second resistances, a first amplification transistor coupled to the first input node, the first resistance, and the first intermediate node and a second amplification transistor coupled to the second input node, the second resistance, and the second intermediate node. The circuit may also include a first active device coupled to the first output node and the first intermediate node, a second active device coupled to the second output node and the second intermediate node, a first output transistor coupled to the first output node and configured to conduct based on a second intermediate signal on the second intermediate node, and a second output transistor coupled to the second output node and configured to conduct based on a first intermediate signal on the first intermediate node.Type: GrantFiled: June 27, 2014Date of Patent: August 2, 2016Assignee: FINISAR CORPORATIONInventors: Arik Zafrany, Georgios Kalogerakis
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Publication number: 20150381172Abstract: A circuit may include first and second input nodes, first and second output nodes, first and second intermediate nodes, first and second resistances, a first amplification transistor coupled to the first input node, the first resistance, and the first intermediate node and a second amplification transistor coupled to the second input node, the second resistance, and the second intermediate node. The circuit may also include a first active device coupled to the first output node and the first intermediate node, a second active device coupled to the second output node and the second intermediate node, a first output transistor coupled to the first output node and configured to conduct based on a second intermediate signal on the second intermediate node, and a second output transistor coupled to the second output node and configured to conduct based on a first intermediate signal on the first intermediate node.Type: ApplicationFiled: June 27, 2014Publication date: December 31, 2015Inventors: Arik ZAFRANY, Georgios KALOGERAKIS
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Patent number: 9148129Abstract: A circuit may include an input node configured to receive a signal and an output node configured to be coupled to a load. The circuit may also include a first circuit coupled between the input node and the output node, the first circuit being configured to receive the signal and drive the signal on the output node at a first voltage. The circuit may also include a signal adjust circuit configured to adjust a current of the signal driven by the first circuit. The signal adjust circuit may be configured to apply a first current adjustment to adjust the current of the signal at one but not both of a falling edge of the signal or a rising edge of the signal.Type: GrantFiled: June 7, 2013Date of Patent: September 29, 2015Assignee: FINISAR CORPORATIONInventors: Jason Miao, Arik Zafrany, Georgios Kalogerakis
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Publication number: 20140361813Abstract: A circuit may include an input node configured to receive a signal and an output node configured to be coupled to a load. The circuit may also include a first circuit coupled between the input node and the output node, the first circuit being configured to receive the signal and drive the signal on the output node at a first voltage. The circuit may also include a signal adjust circuit configured to adjust a current of the signal driven by the first circuit. The signal adjust circuit may be configured to apply a first current adjustment to adjust the current of the signal at one but not both of a falling edge of the signal or a rising edge of the signal.Type: ApplicationFiled: June 7, 2013Publication date: December 11, 2014Inventors: Jason Miao, Arik Zafrany, Georgios Kalogerakis