Patents by Inventor Aritra Dey

Aritra Dey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flicker noise elimination in a double balanced mixer DC bias circuit
    Patent number: 11381203
    Abstract: A transmitter that reduces 3rd order harmonic (HD3) and inter modulation distortion (IMD3) for a gm stage of a mixer while reducing flicker noise is disclosed. The transmitter may include a balanced mixer, a transconductance stage connected to the mixer, and a bias circuit. The bias circuit may include a programmable current source configured to provide a reference current. Further, the bias circuit may include a replica circuit configured to replicate a DC signal of the transconductance stage. The bias circuit may also include a bias transistor configured to level shift a bias signal obtained from a signal source based on the reference current and the DC signal of the transconductance stage as determined from the replica circuit.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 5, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Aritra Dey, Tolga Pamir, Mostafa Haroun
  • FLICKER NOISE ELIMINATION IN A DOUBLE BALANCED MIXER DC BIAS CIRCUIT
    Publication number: 20220045646
    Abstract: A transmitter that reduces 3rd order harmonic (HD3) and inter modulation distortion (IMD3) for a gm stage of a mixer while reducing flicker noise is disclosed. The transmitter may include a balanced mixer, a transconductance stage connected to the mixer, and a bias circuit. The bias circuit may include a programmable current source configured to provide a reference current. Further, the bias circuit may include a replica circuit configured to replicate a DC signal of the transconductance stage. The bias circuit may also include a bias transistor configured to level shift a bias signal obtained from a signal source based on the reference current and the DC signal of the transconductance stage as determined from the replica circuit.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 10, 2022
    Inventors: Aritra Dey, Tolga Pamir, Mostafa Haroun
  • Source follower-based sallen-key architecture
    Patent number: 10778189
    Abstract: Systems and methods for improving source-follower-based Sallen-Key architectures are disclosed. In particular, systems and methods for circumventing the non-idealities associated with source-follower-based Sallen-Key biquad filters when used in either baseband signal or radiofrequency paths. The systems and methods disclosed herein present power-efficient, cost-efficient solutions that can be implemented in a reduced area of a circuit.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: September 15, 2020
    Assignee: ANALOG DEVICES, INC.
    Inventor: Aritra Dey
  • Complementary biasing circuits and related methods
    Patent number: 9035692
    Abstract: Embodiments of complementary biasing circuits and related methods are described herein. Other embodiments and related implementations are also disclosed herein.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 19, 2015
    Assignee: Arizona Board of Regents, a body corporate of the State of Arizona, Acting for and on Behalf of Arizona State University
    Inventor: Aritra Dey
  • COMPLEMENTARY BIASING CIRCUITS AND RELATED METHODS
    Publication number: 20140070868
    Abstract: Embodiments of complementary biasing circuits and related methods are described herein. Other embodiments and related implementations are also disclosed herein.
    Type: Application
    Filed: March 13, 2013
    Publication date: March 13, 2014
    Applicant: Arizona Board of Regents, a body corporate of the State of Arizona Acting for and on behalf of Arizo
    Inventor: Aritra Dey
  • Amplifiers with depletion and enhancement mode thin film transistors and related methods
    Patent number: 8319561
    Abstract: Embodiments of amplifiers with depletion and enhancement mode thin film transistors are disclosed herein. Other examples, devices, and related methods are also disclosed herein.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: November 27, 2012
    Assignee: Arizona Board of Regents, a body corporate of the State of Arizona, Acting for and on behalf of Arizona State University
    Inventors: Sameer M. Venugopal, Aritra Dey, David R. Allee
  • AMPLIFIERS WITH DEPLETION AND ENHANCEMENT MODE THIN FILM TRANSISTORS AND RELATED METHODS
    Publication number: 20120206207
    Abstract: Embodiments of amplifiers with depletion and enhancement mode thin film transistors are disclosed herein. Other examples, devices, and related methods are also disclosed herein.
    Type: Application
    Filed: March 2, 2012
    Publication date: August 16, 2012
    Applicants: Arizona State University
    Inventors: Sameer M. Venugopal, Aritra Dey, David R. Allee