Abstract: A circuit arrangement including a test-traffic generator, and adapted to communicate test-traffic onto a digital data path having other traffic sources. A first embodiment includes a data-generation circuit, a memory arrangement, state machine circuitry, and a status and feedback circuit. The memory arrangement stores a plurality of programmable commands indicative the type, pattern and behavior-in-time of the test-traffic. The data-generation circuit provides a data stream to the state machine circuitry, where the state machine assembles portions of the data stream into test-traffic having type, pattern and behavior-in-time characteristics selected responsive to the programmable commands. The state machine generates test-traffic on the digital data path. The status and feedback circuit monitors the digital data path for test-traffic, verifies the test-traffic against the data stream, and generates a feedback signal indicative of test-traffic quality or throughput.

Abstract: In one example embodiment, data is transferred at high speeds over a parallel data bus without loss of data integrity by transferring the data encoded with the quantity of ones relatively the same as the quantity of zeroes. Consistent with one embodiment of the present invention, a bus-interface circuit encodes a set of X data bits into a set of Y data bits, where Y is greater than X. The encoding is implemented to approximately balance the number of ones and the number of zeroes in each set to be transmitted. A specific example application involves encoding the set of X data bits so that there is a balanced number of ones and zeroes in the set of Y data bits. In certain applications, the present invention is implemented to reduce current flow between transmitting and receiving modules and thereby reduce EMI, reduce the number of power pins required for the bus interface, and/or reduce the I/O delay and the skew from voltage sag in the signals passed over the parallel data bus.

Abstract: In one example embodiment, data is transferred at high speeds over a parallel data bus without loss of data integrity by transferring the data encoded with the quantity of ones relatively the same as the quantity of zeroes. Consistent with one embodiment of the present invention, a bus-interface circuit encodes a set of X data bits into a set of Y data bits, where Y is greater than X. The encoding is implemented to approximately balance the number of ones and the number of zeroes in each set to be transmitted. A specific example application involves encoding the set of X data bits so that there is a balanced number of ones and zeroes in the set of Y data bits. In certain applications, the present invention is implemented to reduce current flow between transmitting and receiving modules and thereby reduce EMI, reduce the number of power pins required for the bus interface, and/or reduce the I/O delay and the skew from voltage sag in the signals passed over the parallel data bus.

Abstract: A circuit arrangement including a test-traffic generator, and adapted to communicate test-traffic onto a digital data path having other traffic sources. A first embodiment includes a data-generation circuit, a memory arrangement, state machine circuitry, and a status and feedback circuit. The memory arrangement stores a plurality of programmable commands indicative the type, pattern and behavior-in-time of the test-traffic. The data-generation circuit provides a data stream to the state machine circuitry, where the state machine assembles portions of the data stream into test-traffic having type, pattern and behavior-in-time characteristics selected responsive to the programmable commands. The state machine generates test-traffic on the digital data path. The status and feedback circuit monitors the digital data path for test-traffic, verifies the test-traffic against the data stream, and generates a feedback signal indicative of test-traffic quality or throughput.