Patents by Inventor Arjan Breeschoten

Arjan Breeschoten has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10684779
    Abstract: The disclosure relates to a memory access unit. One example embodiment is a memory access unit, for providing read-access to read an item from an arbitrary location in a physical memory, independently of addressable locations of the physical memory. The item includes a first number of bits and each addressable location of the physical memory includes a second number of bits. The second number of bits is different from the first number of bits. The memory access unit includes an address input, an address interpreter, an address output, a memory output, a data formatter, and a data output.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: June 16, 2020
    Assignees: IMEC VZW, Stichting IMEC Nederland
    Inventors: Victor Van Acht, George Tsouhlarakis, Mario Konijnenburg, Arjan Breeschoten
  • Publication number: 20170147210
    Abstract: The disclosure relates to a memory access unit. One example embodiment is a memory access unit, for providing read-access to read an item from an arbitrary location in a physical memory, independently of addressable locations of the physical memory. The item includes a first number of bits and each addressable location of the physical memory includes a second number of bits. The second number of bits is different from the first number of bits. The memory access unit includes an address input, an address interpreter, an address output, a memory output, a data formatter, and a data output.
    Type: Application
    Filed: November 11, 2016
    Publication date: May 25, 2017
    Applicants: IMEC VZW, Stichting IMEC Nederland
    Inventors: Victor Van Acht, George Tsouhlarakis, Mario Konijnenburg, Arjan Breeschoten
  • Patent number: 8261154
    Abstract: A continuous redundancy check method and apparatus receives (110) at least one data bit of a block's payload, calculates (120) a partial redundancy check value using the at least one data bit, compares (130) the partial redundancy check value with a reference value, and stores (134, 138) in an index an indication of whether the calculated redundancy check value matched the reference value. Meanwhile, the at least one data bit is also stored (140) in a data memory. As additional data bits of the payload are received, cumulative partial redundancy check values are calculated and compared to the reference value. When the complete payload has been stored (140), the index is analyzed (160, 165) to determine if a block error has been detected by the redundancy check functions. This continuous redundancy check method and apparatus allows a receiver to quickly determine whether a block error has occurred, especially when there may be padding (or dummy) bits in the block's payload.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: September 4, 2012
    Assignee: Motorola Mobility LLC
    Inventors: Maarten Vermeiden, Albert Bredewoud, Arjan Breeschoten, Wim J. Diepstraten
  • Publication number: 20090125779
    Abstract: A continuous redundancy check method and apparatus receives (110) at least one data bit of a block's payload, calculates (120) a partial redundancy check value using the at least one data bit, compares (130) the partial redundancy check value with a reference value, and stores (134, 138) in an index an indication of whether the calculated redundancy check value matched the reference value. Meanwhile, the at least one data bit is also stored (140) in a data memory. As additional data bits of the payload are received, cumulative partial redundancy check values are calculated and compared to the reference value. When the complete payload has been stored (140), the index is analyzed (160, 165) to determine if a block error has been detected by the redundancy check functions. This continuous redundancy check method and apparatus allows a receiver to quickly determine whether a block error has occurred, especially when there may be padding (or dummy) bits in the block's payload.
    Type: Application
    Filed: November 12, 2007
    Publication date: May 14, 2009
    Applicant: MOTOROLA, INC.
    Inventors: MAARTEN VERMEIDEN, ALBERT BREDEWOUD, ARJAN BREESCHOTEN, WIM J. DIEPSTRATEN