Abstract: A semiconductor device and methods of forming the same include a semiconductive fin protruding vertically from a body region and extending along a first direction, an insulator material above the body region and surrounding a lower portion of the fin, and a gap region between first and second ends of the semiconductive fin where at least a top portion of the semiconductive fin is absent. The device includes current terminals coupled to first and second ends of the fin, and a gate electrode and a gate extension coupled to the fin. The gate electrode surrounds the top portion of the semiconductive fin and is separated from the semiconductive by a gate insulator material. The gate extension has a first end adjacent to the gate electrode and a second end above the body region within the gap region.

Abstract: A surge protection circuit includes a DC trigger circuit that generates a trigger signal when a surge pulse occurs, and a current conducting unit, coupled to the DC trigger circuit, that generates a first clamp voltage as an output voltage of the surge protection circuit and conducts surge currents to ground in response to the trigger signal. The DC trigger circuit includes a surge detection circuit and a first amplification circuit. The surge detection circuit detects if a surge pulse occurs, and triggers the first amplification circuit to generate the trigger signal when the surge detection circuit detects a surge pulse.

Abstract: A surge protection circuit includes a DC trigger circuit that generates a trigger signal when a surge pulse occurs, and a current conducting unit, coupled to the DC trigger circuit, that generates a first clamp voltage as an output voltage of the surge protection circuit and conducts surge currents to ground in response to the trigger signal. The DC trigger circuit includes a surge detection circuit and a first amplification circuit. The surge detection circuit detects if a surge pulse occurs, and triggers the first amplification circuit to generate the trigger signal when the surge detection circuit detects a surge pulse.

Abstract: A field-effect transistor (FET) includes, a first drain, a second drain, a body and a gate region. The gate region has a length, and is configured and arranged to create, in response to a gate voltage, a channel that is in the body, between the first and second drains, and along the length of the gate region. A plurality of body dropdowns are located in the gate region and are spaced along a width of the gate region. Each of the body dropdowns are configured and arranged to provide an electrical contact to the body for biasing purposes.

Abstract: It is described a method for providing an electronic key within an integrated circuit (100) including both a volatile memory (102) and a non-volatile memory (104). The described comprises starting up the integrated circuit (100), reading the logical state of predetermined data storage cells (102a) assigned to the volatile memory (102), which data storage cells (102a) are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and generating an electronic key by using the logical state of the predetermined data storage cells (102a). Preferably, the predetermined data storage cells (102a) are randomly distributed within the volatile memory (102). It is further described an integrated circuit (100) for providing an electronic key.

Abstract: It is described a method for providing an electronic key within an integrated circuit (100) including both a volatile memory (102) and a non-volatile memory (104). The described comprises starting up the integrated circuit (100), reading the logical state of predetermined data storage cells (102a) assigned to the volatile memory (102), which data storage cells (102a) are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and generating an electronic key by using the logical state of the predetermined data storage cells (102a). Preferably, the predetermined data storage cells (102a) are randomly distributed within the volatile memory (102). It is further described an integrated circuit (100) for providing an electronic key.