Patents by Inventor Arjen Mets
Arjen Mets has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10671791Abstract: A computer-implemented method for optimizing microprocessor gates in a microprocessor includes receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor; determining, via the processor, whether a transmission line in the model, if implemented in a physical circuit, would result a signal transmission time less than a predetermined threshold time; applying to the model, via the processor, a proposed gate change to one or more of the plurality of gates; evaluating, via the processor and an area degradation based on the proposed gate change; determining, via the processor, a margin value based on the signal transmission time and an area degradation value; and making, via the processor, a gate change decision based on the margin value.Type: GrantFiled: July 11, 2018Date of Patent: June 2, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. Kazda, Arjen A. Mets, Lakshmi N. Reddy, Cindy S. Washburn, Nancy Y. Zhou
-
Publication number: 20180330039Abstract: A computer-implemented method for optimizing microprocessor gates in a microprocessor includes receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor; determining, via the processor, whether a transmission line in the model, if implemented in a physical circuit, would result a signal transmission time less than a predetermined threshold time; applying to the model, via the processor, a proposed gate change to one or more of the plurality of gates; evaluating, via the processor and an area degradation based on the proposed gate change; determining, via the processor, a margin value based on the signal transmission time and an area degradation value; and making, via the processor, a gate change decision based on the margin value.Type: ApplicationFiled: July 11, 2018Publication date: November 15, 2018Inventors: Michael A. Kazda, Arjen A. Mets, Lakshmi N. Reddy, Cindy S. Washburn, Nancy Y. Zhou
-
Patent number: 10078722Abstract: A computer-implemented method for optimizing microprocessor gates in a microprocessor includes receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor; determining, via the processor, whether a transmission line in the model, if implemented in a physical circuit, would result a signal transmission time less than a predetermined threshold time; applying to the model, via the processor, a proposed gate change to one or more of the plurality of gates; evaluating, via the processor and an area degradation based on the proposed gate change; determining, via the processor, a margin value based on the signal transmission time and an area degradation value; and making, via the processor, a gate change decision based on the margin value.Type: GrantFiled: June 13, 2016Date of Patent: September 18, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. Kazda, Arjen A. Mets, Lakshmi N. Reddy, Cindy S. Washburn, Nancy Y. Zhou
-
Patent number: 9990454Abstract: A system and method for enabling the estimation and mitigation of self-heating in chip designs at a much earlier stage in a design flow. The system and method provides unique characterization of each standard cell in a library for its effective thermal resistance based on the topology and layout of the cell, and brings this per standard cell instance based delta-T to be available for the timing closure tools when completing a synthesized design. Thus, at the timing closure process, the generated design is free of self heating violations. The method computes a unique thermal resistance characterization on per standard cell manner—based on the topology, function and layout of the standard cell, and uses that to compute the deltaT per instance of the design. This information is presented to a violation mitigation tool which changes the power levels of the cells, logic function to mitigate the self heating violations.Type: GrantFiled: June 3, 2016Date of Patent: June 5, 2018Assignee: International Business Machines CorporationInventors: Nagashyamala R. Dhanwada, William W. Dungan, Arun Joseph, Sungjae Lee, Arjen A. Mets, Michael R. Scheuermann, Leon J. Sigal, Richard A. Wachnick, James D. Warnock
-
Publication number: 20170357747Abstract: A computer-implemented method for optimizing microprocessor gates in a microprocessor includes receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor; determining, via the processor, whether a transmission line in the model, if implemented in a physical circuit, would result a signal transmission time less than a predetermined threshold time; applying to the model, via the processor, a proposed gate change to one or more of the plurality of gates; evaluating, via the processor and an area degradation based on the proposed gate change; determining, via the processor, a margin value based on the signal transmission time and an area degradation value; and making, via the processor, a gate change decision based on the margin value.Type: ApplicationFiled: June 13, 2016Publication date: December 14, 2017Inventors: Michael A. Kazda, Arjen A. Mets, Lakshmi N. Reddy, Cindy S. Washburn, Nancy Y. Zhou
-
Publication number: 20170351785Abstract: A system and method for enabling the estimation and mitigation of self-heating in chip designs at a much earlier stage in a design flow. The system and method provides unique characterization of each standard cell in a library for its effective thermal resistance based on the topology and layout of the cell, and brings this per standard cell instance based delta-T to be available for the timing closure tools when completing a synthesized design. Thus, at the timing closure process, the generated design is free of self heating violations. The method computes a unique thermal resistance characterization on per standard cell manner—based on the topology, function and layout of the standard cell, and uses that to compute the deltaT per instance of the design. This information is presented to a violation mitigation tool which changes the power levels of the cells, logic function to mitigate the self heating violations.Type: ApplicationFiled: June 3, 2016Publication date: December 7, 2017Inventors: Nagashyamala R. Dhanwada, William W. Dungan, Arun Joseph, Sungjae Lee, Arjen A. Mets, Michael R. Scheuermann, Leon J. Sigal, Richard A. Wachnick, James D. Warnock
-
Patent number: 9734268Abstract: A system and method to implement an integrated circuit design are described. The method includes obtaining a timing database of current timing slack values based on current cell selection, placement, and routing for a plurality of cycles defined by a plurality of cycle boundaries, each cycle representing devices between a corresponding pair of the plurality of cycle boundaries, identifying candidate cycle boundaries among the plurality of cycle boundaries for slack redistribution, every one of the candidate cycle boundaries being associated with a positive timing slack, and selecting redistribution cycle boundaries among the candidate cycle boundaries. A modified timing database is generated based on redistributing the positive timing slack associated with the redistribution cycle boundaries, and power recovery is performed using the modified timing database to reduce power at one of more of the redistribution cycle boundaries.Type: GrantFiled: August 12, 2015Date of Patent: August 15, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher J. Berry, Yiu-Hing Chan, Arjen A. Mets, Charudhattan Nagarajan, Ricardo H. Nigaglioni, Sourav Saha, Hameedbasha Shaik
-
Patent number: 9684751Abstract: A system and method to implement an integrated circuit design are described. The method includes obtaining a timing database of current timing slack values based on current cell selection, placement, and routing for a plurality of cycles defined by a plurality of cycle boundaries, each cycle representing devices between a corresponding pair of the plurality of cycle boundaries, identifying candidate cycle boundaries among the plurality of cycle boundaries for slack redistribution, every one of the candidate cycle boundaries being associated with a positive timing slack, and selecting redistribution cycle boundaries among the candidate cycle boundaries. A modified timing database is generated based on redistributing the positive timing slack associated with the redistribution cycle boundaries, and power recovery is performed using the modified timing database to reduce power at one of more of the redistribution cycle boundaries.Type: GrantFiled: October 9, 2015Date of Patent: June 20, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher J. Berry, Yiu-Hing Chan, Arjen A. Mets, Charudhattan Nagarajan, Ricardo H. Nigaglioni, Sourav Saha, Hameedbasha Shaik
-
Publication number: 20170046464Abstract: A system and method to implement an integrated circuit design are described. The method includes obtaining a timing database of current timing slack values based on current cell selection, placement, and routing for a plurality of cycles defined by a plurality of cycle boundaries, each cycle representing devices between a corresponding pair of the plurality of cycle boundaries, identifying candidate cycle boundaries among the plurality of cycle boundaries for slack redistribution, every one of the candidate cycle boundaries being associated with a positive timing slack, and selecting redistribution cycle boundaries among the candidate cycle boundaries. A modified timing database is generated based on redistributing the positive timing slack associated with the redistribution cycle boundaries, and power recovery is performed using the modified timing database to reduce power at one of more of the redistribution cycle boundaries.Type: ApplicationFiled: October 9, 2015Publication date: February 16, 2017Inventors: Christopher J. Berry, Yiu-Hing Chan, Arjen A. Mets, Charudhattan Nagarajan, Ricardo H. Nigaglioni, Sourav Saha, Hameedbasha Shaik
-
Publication number: 20170046463Abstract: A system and method to implement an integrated circuit design are described. The method includes obtaining a timing database of current timing slack values based on current cell selection, placement, and routing for a plurality of cycles defined by a plurality of cycle boundaries, each cycle representing devices between a corresponding pair of the plurality of cycle boundaries, identifying candidate cycle boundaries among the plurality of cycle boundaries for slack redistribution, every one of the candidate cycle boundaries being associated with a positive timing slack, and selecting redistribution cycle boundaries among the candidate cycle boundaries. A modified timing database is generated based on redistributing the positive timing slack associated with the redistribution cycle boundaries, and power recovery is performed using the modified timing database to reduce power at one of more of the redistribution cycle boundaries.Type: ApplicationFiled: August 12, 2015Publication date: February 16, 2017Inventors: Christopher J. Berry, Yiu-Hing Chan, Arjen A. Mets, Charudhattan Nagarajan, Ricardo H. Nigaglioni, Sourav Saha, Hameedbasha Shaik
-
Patent number: 7979732Abstract: A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.Type: GrantFiled: July 3, 2007Date of Patent: July 12, 2011Assignee: International Business Machines CorporationInventors: Lawrence D. Curley, John M. Isakson, Arjen Mets, Travis W. Pouarz, Thomas E. Rosser, Kristen M. Tucker
-
Publication number: 20090013206Abstract: A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.Type: ApplicationFiled: July 3, 2007Publication date: January 8, 2009Inventors: Lawrence D. Curley, John M. Isakson, Arjen Mets, Travis W. Pouarz, Thomas E. Rosser, Kristen M. Tucker