Abstract: The present invention facilitates efficient and effective information storage device operations. In one embodiment, a system comprises: a plurality of processing cores configured to process information and a debug system coupled to the plurality of cores. The plurality of processing cores are configured to perform respective test operations on the respective processing cores. The debug system is configured to gather results of the test operations on a flexible compaction basis, wherein a compacted indication of a passing test result is available at a debug cluster basis and compacted indications of a failed test result available at the debug cluster basis are further resolved to identify a failing processing core within the cluster. The processing cores are organized in clusters, wherein a set comprising more than one of the plurality of processing cores and less than all of the processing cores is considered a cluster.

Abstract: The present invention facilitates efficient and effective information storage device operations. In one embodiment, a system comprises: a plurality of processing cores configured to process information and a debug system coupled to the plurality of cores. The plurality of processing cores are configured to perform respective test operations on the respective processing cores. The debug system is configured to gather results of the test operations on a flexible compaction basis, wherein a compacted indication of a passing test result is available at a debug cluster basis and compacted indications of a failed test result available at the debug cluster basis are further resolved to identify a failing processing core within the cluster. The processing cores are organized in clusters, wherein a set comprising more than one of the plurality of processing cores and less than all of the processing cores is considered a cluster.

Abstract: An integrated circuit (IC) protection circuit can include a reconfigurable block that receives a seed value from a tamper-proof memory and generates a dynamic key; an authentication block that receives the dynamic key from the reconfigurable block and taint bits from a scan chain to generate an authentication signature; and an encryptor that encrypts a test pattern response on the scan chain if a mismatch is found between the authentication signature and a test pattern embedded signature.

Abstract: A system for evaluating fault criticality using machine learning includes a first machine learning module that is trained on a subset of a circuit and used for evaluating whether a node in a netlist of the entire circuit is a critical node, and a second machine learning module specialized to minimize classification errors in nodes predicted as benign. A generative adversarial network can be used to generate synthetic test escape data to supplement data used to train the second machine learning module.

Abstract: An integrated circuit (IC) protection circuit can include a reconfigurable block that receives a seed value from a tamper-proof memory and generates a dynamic key; an authentication block that receives the dynamic key from the reconfigurable block and taint bits from a scan chain to generate an authentication signature; and an encryptor that encrypts a test pattern response on the scan chain if a mismatch is found between the authentication signature and a test pattern embedded signature.

Abstract: A method for identifying observation points for integrated circuit (IC) testing includes receiving a netlist for an IC that includes a first subcircuit and a second subcircuit; determining, from the netlist, one or more observation points, each determined observation point corresponding to an output node which provides observability, into at least the first subcircuit, of an effective number of gates above a specified threshold; and inserting a design for test element into a layout file of the IC at each determined observation point. Observation points can be determined by transforming the netlist into a node graph; assigning a same initial value to a value field of each node; and propagating values in the value fields of the nodes until all nodes with a succeeding edge have a value of zero in their value fields.

Abstract: A method of fault criticality assessment using neural twins includes converting a netlist into a neural twin by replacing each circuit element of the netlist with a neural-network-readable cell equivalent; and replacing each wire with a neural connection. Bias value adders are inserted at locations in the neural twin; and these bias value adders are used to apply a bias that represents a perturbation in the signal propagated by that connection. For each perturbed bias at a corresponding site selected to be perturbed, a loss value is calculated for the neural twin; and the site is classified, using a neural-twin-trained classifier, as critical or benign based on that loss value.

Abstract: Systems and methods are provided for testing many-core processors consisting of processing element cores. The systems and methods can include grouping the processing elements according to the dataflow of the many-core processor. Each group can include a processing element that only receives inputs from other processing elements in the group. After grouping the processing elements, test information can be provided in parallel to each group. The test information can be configured to ensure a desired degree of test coverage for the processing element that that only receives inputs from other processing elements in the group. Each group can perform testing operations in parallel to generate test results. The test results can be read out of each group. The processing elements can then be regrouped according to the dataflow of the many-core processor and the testing can be repeated to achieve a target test coverage.

Abstract: A method of fault criticality assessment using a k-tier graph convolution network (GCN) framework, where k?2, includes generating a graph from a netlist of a processing element implementing a target hardware architecture having an applied domain-specific use-case, wherein a logic gate is represented in the graph as a node and a signal path between two logic gates is represented in the netlist-graph as an edge; evaluating functional criticality of unlabeled nodes of the graph using a trained first GCN, and evaluating nodes classified as benign by the trained first GCN using a trained second GCN to identify misclassified nodes.

Abstract: A system for evaluating fault criticality using machine learning includes a first machine learning module that is trained on a subset of a circuit and used for evaluating whether a node in a netlist of the entire circuit is a critical node, and a second machine learning module specialized to minimize classification errors in nodes predicted as benign. A generative adversarial network can be used to generate synthetic test escape data to supplement data used to train the second machine learning module.

Abstract: A method for identifying observation points for integrated circuit (IC) testing includes receiving a netlist for an IC that includes a first subcircuit and a second subcircuit; determining, from the netlist, one or more observation points, each determined observation point corresponding to an output node which provides observability, into at least the first subcircuit, of an effective number of gates above a specified threshold; and inserting a design for test element into a layout file of the IC at each determined observation point. Observation points can be determined by transforming the netlist into a node graph; assigning a same initial value to a value field of each node; and propagating values in the value fields of the nodes until all nodes with a succeeding edge have a value of zero in their value fields.

Abstract: A method for testing a many-core processor comprises grouping a plurality of cores in the processor into a plurality of super cores, wherein each super core comprises one or more scan chains that propagate through a respective super core. Further, the method comprises grouping the plurality of super cores into a plurality of clusters. The method also comprises comparing one or more scan chain outputs of respective super cores in each cluster using a network of XOR and OR gates to generate a single bit fault signature for each scan chain in a respective cluster and compacting the single bit fault signatures for each scan chain using a hybrid of spatial and temporal compactors to generate a single bit fault signature for each cluster. The method also comprises method of using a cost function to obtain hierarchical parameters to achieve optimized ATPG effort, area overhead and test time.

Abstract: Systems and methods are provided for testing many-core processors consisting of processing element cores. The systems and methods can include grouping the processing elements according to the dataflow of the many-core processor. Each group can include a processing element that only receives inputs from other processing elements in the group. After grouping the processing elements, test information can be provided in parallel to each group. The test information can be configured to ensure a desired degree of test coverage for the processing element that that only receives inputs from other processing elements in the group. Each group can perform testing operations in parallel to generate test results. The test results can be read out of each group. The processing elements can then be regrouped according to the dataflow of the many-core processor and the testing can be repeated to achieve a target test coverage.

Abstract: A method for testing a many-core processor comprises grouping a plurality of cores in the processor into a plurality of super cores, wherein each super core comprises one or more scan chains that propagate through a respective super core. Further, the method comprises grouping the plurality of super cores into a plurality of clusters. The method also comprises comparing one or more scan chain outputs of respective super cores in each cluster using a network of XOR and OR gates to generate a single bit fault signature for each scan chain in a respective cluster and compacting the single bit fault signatures for each scan chain using a hybrid of spatial and temporal compactors to generate a single bit fault signature for each cluster. The method also comprises method of using a cost function to obtain hierarchical parameters to achieve optimized ATPG effort, area overhead and test time.