Patents by Inventor Arjun Kapoor

Arjun Kapoor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9965186
    Abstract: A memory device and techniques for its operation are presented. After operating on power received from a host, the memory device determines that it is no longer receiving host power and, in response, activates a power source on the memory device itself. Using this reserve power, the memory device can then perform data management operations. The techniques can also be applied to a digital appliance having a non-volatile memory. The memory device or digital appliance can prioritize its memory management operation during the host/user operating window based on the ability to perform these operations outside of the host/user operating window.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: May 8, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Arjun Kapoor, Rajeev Nagabhirava, Dhaval Parikh
  • Patent number: 9690734
    Abstract: A plurality of data links interconnects a number (N) of nodes of a large-scale, parallel system with minimum data transfer latency. A maximum number (K) of the data links connect each node to the other nodes. The number (N) of the nodes is related to the maximum number (K) of the data links by the expression: N=2K. An average distance (A) of the shortest distances between all pairs of the nodes, and a diameter (D), which is a largest of the shortest distances, are minimized.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: June 27, 2017
    Inventor: Arjun Kapoor
  • Publication number: 20170177231
    Abstract: A memory device and techniques for its operation are presented. After operating on power received from a host, the memory device determines that it is no longer receiving host power and, in response, activates a power source on the memory device itself. Using this reserve power, the memory device can then perform data management operations. The techniques can also be applied to a digital appliance having a non-volatile memory. The memory device or digital appliance can prioritize its memory management operation during the host/user operating window based on the ability to perform these operations outside of the host/user operating window.
    Type: Application
    Filed: March 7, 2017
    Publication date: June 22, 2017
    Inventors: Arjun Kapoor, Rajeev Nagabhirava, Dhaval Parikh
  • Patent number: 9607664
    Abstract: A memory device and techniques for its operation are presented. After operating on power received from a host, the memory device determines that it is no longer receiving host power and, in response, activates a power source on the memory device itself. Using this reserve power, the memory device can then perform data management operations. The techniques can also be applied to a digital appliance having a non-volatile memory. The memory device or digital appliance can prioritize its memory management operation during the host/user operating window based on the ability to perform these operations outside of the host/user operating window.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: March 28, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Arjun Kapoor, Rajeev Nagabhirava, Dhaval Parikh
  • Publication number: 20160070668
    Abstract: A plurality of data links interconnects a number (N) of nodes of a large-scale, parallel system with minimum data transfer latency. A maximum number (K) of the data links connect each node to the other nodes. The number (N) of the nodes is related to the maximum number (K) of the data links by the expression: N=2K. An average distance (A) of the shortest distances between all pairs of the nodes, and a diameter (D), which is a largest of the shortest distances, are minimized.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 10, 2016
    Inventor: Arjun KAPOOR
  • Patent number: 9063732
    Abstract: Systems and methods are disclosed for limiting power consumption of a non-volatile memory (NVM) using a power limiting scheme that distributes a number of concurrent NVM operations over time. This provides a “current consumption cap” that fixes an upper limit of current consumption for the NVM, thereby eliminating peak power events. In one embodiment, power consumption of a NVM can be limited by receiving data suitable for use as a factor in adjusting a current threshold from at least one of a plurality of system sources. The current threshold can be less than a peak current capable of being consumed by the NVM and can be adjusted based on the received data. A power limiting scheme can be used that limits the number of concurrent NVM operations performed so that a cumulative current consumption of the NVM does not exceed the adjusted current threshold.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: June 23, 2015
    Assignee: APPLE INC.
    Inventors: Matthew J. Byom, Vadim Khmelnitsky, Hugo B. Fiennes, Arjun Kapoor
  • Publication number: 20140068296
    Abstract: Systems and methods are disclosed for limiting power consumption of a non-volatile memory (NVM) using a power limiting scheme that distributes a number of concurrent NVM operations over time. This provides a “current consumption cap” that fixes an upper limit of current consumption for the NVM, thereby eliminating peak power events. In one embodiment, power consumption of a NVM can be limited by receiving data suitable for use as a factor in adjusting a current threshold from at least one of a plurality of system sources. The current threshold can be less than a peak current capable of being consumed by the NVM and can be adjusted based on the received data. A power limiting scheme can be used that limits the number of concurrent NVM operations performed so that a cumulative current consumption of the NVM does not exceed the adjusted current threshold.
    Type: Application
    Filed: November 11, 2013
    Publication date: March 6, 2014
    Applicant: Apple Inc.
    Inventors: Matthew J. Byom, Vadim Khmelnitsky, Hugo B. Fiennes, Arjun Kapoor
  • Patent number: 8583947
    Abstract: Systems and methods are disclosed for limiting power consumption of a non-volatile memory (NVM) using a power limiting scheme that distributes a number of concurrent NVM operations over time. This provides a “current consumption cap” that fixes an upper limit of current consumption for the NVM, thereby eliminating peak power events. In one embodiment, power consumption of a NVM can be limited by receiving data suitable for use as a factor in adjusting a current threshold from at least one of a plurality of system sources. The current threshold can be less than a peak current capable of being consumed by the NVM and can be adjusted based on the received data. A power limiting scheme can be used that limits the number of concurrent NVM operations performed so that a cumulative current consumption of the NVM does not exceed the adjusted current threshold.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: November 12, 2013
    Assignee: Apple Inc.
    Inventors: Matthew Byom, Vadim Khmelnitsky, Hugo Fiennes, Arjun Kapoor
  • Publication number: 20130290606
    Abstract: Systems and methods are disclosed for power management of a system having non-volatile memory (“NVM”). One or more controllers of the system can optimally turn modules on or off and/or intelligently adjust the operating speeds of modules and interfaces of the system based on the type of incoming commands and the current conditions of the system. This can result in optimal system performance and reduced system power consumption.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Applicant: Apple Inc.
    Inventors: Victor E. Alessi, Nicholas C. Seroff, Arjun Kapoor, Nir Jacob Wakrat, Anthony Fai
  • Patent number: 8555095
    Abstract: Systems and methods are disclosed for limiting power consumption of a non-volatile memory (NVM) using a power limiting scheme that distributes a number of concurrent NVM operations over time. This provides a “current consumption cap” that fixes an upper limit of current consumption for the NVM, thereby eliminating peak power events. In one embodiment, power consumption of a NVM can be limited by receiving data suitable for use as a factor in adjusting a current threshold from at least one of a plurality of system sources. The current threshold can be less than a peak current capable of being consumed by the NVM and can be adjusted based on the received data. A power limiting scheme can be used that limits the number of concurrent NVM operations performed so that a cumulative current consumption of the NVM does not exceed the adjusted current threshold.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: October 8, 2013
    Assignee: Apple Inc.
    Inventors: Matthew Byom, Vadim Khmelnitsky, Hugo Fiennes, Arjun Kapoor
  • Patent number: 8533558
    Abstract: A method includes initiating a compression operation to compress data to be stored in a group of storage elements at a memory device that includes an error correction coding (ECC) engine. The method includes selecting one of a first mode of the ECC engine to generate a first number of parity bits and a second mode of the ECC engine to generate a second number of parity bits based on an extent of compression of the data. The method also includes encoding the compressed data to generate parity bits corresponding to the compressed data and storing the compressed data and the parity bits to the group of storage elements according to a page format that includes a data portion and a parity portion. The compressed data is stored in the data portion and at least some of the parity bits are stored in the parity portion.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: September 10, 2013
    Assignee: Sandisk Technologies Inc.
    Inventors: Damian Pablo Yurzola, Rajeev Nagabhirava, Arjun Kapoor, Itai Dror, Annie Chi-San Chang, Peter Hwang, Jian Chen
  • Patent number: 8533564
    Abstract: A controller coupled to a memory array includes an error correction coding (ECC) engine and an ECC enhancement compression module coupled to the ECC engine. The ECC enhancement compression module is configured to receive and compress control data to be provided to the ECC engine to be encoded. Compressed encoded control data generated at the ECC engine is stored as a codeword at the memory array.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: September 10, 2013
    Assignee: Sandisk Technologies Inc.
    Inventors: Damian Pablo Yurzola, Rajeev Nagabhirava, Arjun Kapoor, Itai Dror
  • Patent number: 8522055
    Abstract: Systems and methods are disclosed for validating a non-volatile memory (NVM) package for use in an electronic device before it is incorporated into the device. A NVM package may be validated by determining its power consumption profile, and if the profile meets predetermined criteria, that NVM package may be qualified for use in an electronic system. The power consumption profile may be obtained by issuing commands, such as read commands, to the NVM package to simultaneously access each die of the NVM package to invoke a maximum power consumption event. During this event, power consumption by the NVM package can be monitored and analyzed to determine whether the NVM package qualifies for use in an electronic device.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: August 27, 2013
    Assignee: Apple Inc.
    Inventors: Matthew Byom, Hugo Fiennes, Arjun Kapoor
  • Patent number: 8495402
    Abstract: Systems and methods are disclosed for limiting power consumption of a non-volatile memory (NVM) using a power limiting scheme that distributes a number of concurrent NVM operations over time. This provides a “current consumption cap” that fixes an upper limit of current consumption for the NVM, thereby eliminating peak power events. In one embodiment, power consumption of a NVM can be limited by receiving data suitable for use as a factor in adjusting a current threshold from at least one of a plurality of system sources. The current threshold can be less than a peak current capable of being consumed by the NVM and can be adjusted based on the received data. A power limiting scheme can be used that limits the number of concurrent NVM operations performed so that a cumulative current consumption of the NVM does not exceed the adjusted current threshold.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: July 23, 2013
    Assignee: Apple Inc.
    Inventors: Matthew Byom, Vadim Khmelnitsky, Hugo Fiennes, Arjun Kapoor
  • Publication number: 20130031009
    Abstract: An ad-hoc cash-dispensing network that allows users to efficiently exchange cash is provided. The ad-hoc cash-dispensing network includes a cash-dispensing server, a network, and a plurality of client terminals that connect to the cash-dispending server through the network. The user of a client terminal sends a request for cash to the cash-dispensing server. The request for cash includes the location of the client terminal. Based on this location, the cash-dispensing server locates one or more other users that are close/proximate to the requesting user and verifies that at least one of these proximate users is willing and able to provide the requested amount of cash. Following the transfer of cash between the parties, the requesting user's account is charged for the service while the providing user's account is credited for the service.
    Type: Application
    Filed: July 28, 2011
    Publication date: January 31, 2013
    Applicant: Apple Inc.
    Inventors: Arjun Kapoor, Nir Wakrat, Anthony Fai
  • Publication number: 20120023346
    Abstract: Systems and methods are disclosed for limiting power consumption of a non-volatile memory (NVM) using a power limiting scheme that distributes a number of concurrent NVM operations over time. This provides a “current consumption cap” that fixes an upper limit of current consumption for the NVM, thereby eliminating peak power events. In one embodiment, power consumption of a NVM can be limited by receiving data suitable for use as a factor in adjusting a current threshold from at least one of a plurality of system sources. The current threshold can be less than a peak current capable of being consumed by the NVM and can be adjusted based on the received data. A power limiting scheme can be used that limits the number of concurrent NVM operations performed so that a cumulative current consumption of the NVM does not exceed the adjusted current threshold.
    Type: Application
    Filed: July 26, 2010
    Publication date: January 26, 2012
    Applicant: Apple Inc.
    Inventors: Matthew Byom, Vadim Khmelnitsky, Hugo Fiennes, Arjun Kapoor
  • Publication number: 20120023347
    Abstract: Systems and methods are disclosed for limiting power consumption of a non-volatile memory (NVM) using a power limiting scheme that distributes a number of concurrent NVM operations over time. This provides a “current consumption cap” that fixes an upper limit of current consumption for the NVM, thereby eliminating peak power events. In one embodiment, power consumption of a NVM can be limited by receiving data suitable for use as a factor in adjusting a current threshold from at least one of a plurality of system sources. The current threshold can be less than a peak current capable of being consumed by the NVM and can be adjusted based on the received data. A power limiting scheme can be used that limits the number of concurrent NVM operations performed so that a cumulative current consumption of the NVM does not exceed the adjusted current threshold.
    Type: Application
    Filed: December 16, 2010
    Publication date: January 26, 2012
    Applicant: Apple Inc.
    Inventors: Matthew Byom, Vadim Khmelnitsky, Hugo Fiennes, Arjun Kapoor
  • Publication number: 20120023348
    Abstract: Systems and methods are disclosed for limiting power consumption of a non-volatile memory (NVM) using a power limiting scheme that distributes a number of concurrent NVM operations over time. This provides a “current consumption cap” that fixes an upper limit of current consumption for the NVM, thereby eliminating peak power events. In one embodiment, power consumption of a NVM can be limited by receiving data suitable for use as a factor in adjusting a current threshold from at least one of a plurality of system sources. The current threshold can be less than a peak current capable of being consumed by the NVM and can be adjusted based on the received data. A power limiting scheme can be used that limits the number of concurrent NVM operations performed so that a cumulative current consumption of the NVM does not exceed the adjusted current threshold.
    Type: Application
    Filed: December 16, 2010
    Publication date: January 26, 2012
    Applicant: Apple Inc.
    Inventors: Matthew Byom, Vadim Khmelnitsky, Hugo Fiennes, Arjun Kapoor
  • Publication number: 20120023356
    Abstract: Systems and methods are disclosed for validating a non-volatile memory (NVM) package for use in an electronic device before it is incorporated into the device. A NVM package may be validated by determining its power consumption profile, and if the profile meets predetermined criteria, that NVM package may be qualified for use in an electronic system. The power consumption profile may be obtained by issuing commands, such as read commands, to the NVM package to simultaneously access each die of the NVM package to invoke a maximum power consumption event. During this event, power consumption by the NVM package can be monitored and analyzed to determine whether the NVM package qualifies for use in an electronic device.
    Type: Application
    Filed: July 26, 2010
    Publication date: January 26, 2012
    Applicant: Apple Inc.
    Inventors: Matthew Byom, Hugo Fiennes, Arjun Kapoor
  • Publication number: 20110154158
    Abstract: A method includes initiating a compression operation to compress data to be stored in a group of storage elements at a memory device that includes an error correction coding (ECC) engine. The method includes selecting one of a first mode of the ECC engine to generate a first number of parity bits and a second mode of the ECC engine to generate a second number of parity bits based on an extent of compression of the data. The method also includes encoding the compressed data to generate parity bits corresponding to the compressed data and storing the compressed data and the parity bits to the group of storage elements according to a page format that includes a data portion and a parity portion. The compressed data is stored in the data portion and at least some of the parity bits are stored in the parity portion.
    Type: Application
    Filed: November 29, 2010
    Publication date: June 23, 2011
    Applicant: SANDISK CORPORATION
    Inventors: DAMIAN PABLO YURZOLA, RAJEEV NAGABHIRAVA, ARJUN KAPOOR, ITAI DROR, ANNIE CHI-SAN CHANG, PETER HWANG, JIAN CHEN