Abstract: According to an exemplary embodiment, a method for fabricating a frontside through-wafer via in a processed wafer includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the processed wafer. The method further includes extending the through-wafer via opening through a substrate to a target depth. The method further includes forming a first conductive layer in the through-wafer via opening and over a through-wafer via pad, which is situated over the at least one interlayer dielectric layer. The first conductive layer in the through-wafer via opening forms an electrical connection between the substrate and the through-wafer via pad. The method further includes forming a second conductive layer on the backside surface of the processed wafer, where the second conductive layer is in electrical contact with the first conductive layer and the substrate.

Abstract: According to an exemplary embodiment, a method for fabricating a top conductive layer in a semiconductor die includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the semiconductor die. The method further includes extending the through-wafer via opening through a substrate of the semiconductor die to reach a target depth. The method further includes forming a through-wafer via conductive layer in the through-wafer via opening, and concurrently forming the top conductive layer over an exposed top metal segment.

Abstract: According to an exemplary embodiment, a method for fabricating a top conductive layer in a semiconductor die includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the semiconductor die. The method further includes extending the through-wafer via opening through a substrate of the semiconductor die to reach a target depth. The method further includes forming a through-wafer via conductive layer in the through-wafer via opening, and concurrently forming the top conductive layer over an exposed top metal segment.

Abstract: According to an exemplary embodiment, a liquid crystal on silicon (LCoS) structure includes a number of pixel electrodes overlying an interlayer dielectric, where diagonally adjacent pixel electrodes are separated by a gap. The LCoS structure further includes a self-planarizing passivation dielectric situated over the pixel electrodes and in the gap, where the self-planarizing passivation dielectric has a selected thickness. The self-planarizing passivation dielectric can be an Oxide-Nitride-Oxide (ONO) stack. The selected thickness of the self-planarizing passivation dielectric causes the self-planarizing passivation dielectric to have a substantially planar top surface. In one embodiment, the thickness of the self-planarizing passivation dielectric can be approximately equal to twice a width of the gap.

Abstract: According to one embodiment, a structure comprises an electrode of a lower MIM capacitor situated in a first interconnect metal layer of a semiconductor die. The structure further comprises a shared electrode of the lower MIM capacitor and an upper MIM capacitor. The structure further comprises an electrode of the upper MIM capacitor situated over the shared electrode. The electrode of the upper MIM capacitor is coupled to the electrode of the lower MIM capacitor through vias and a second interconnect metal layer. In one embodiment, the electrode of the upper MIM capacitor can be divided into two or more segments to allow additional paths for connectivity to reduce the resistance of an electrode of the composite MIM capacitor. In other embodiments, a method for fabricating various embodiments of the composite MIM capacitor is disclosed.

Abstract: A disclosed method for fabricating a structure in a semiconductor die comprises steps of implanting a deep N well in a substrate, depositing an epitaxial layer over the substrate, and forming a P well and a lateral isolation N well over the deep N well, wherein the lateral isolation N well and the P well are fabricated in the substrate and the epitaxial layer, and wherein the lateral isolation N well laterally surrounds the P well, and wherein the deep N well and the lateral isolation N well electrically isolate the P well. Implanting a deep N well can comprise steps of depositing a screen oxide layer over the substrate, forming a mask over the screen oxide layer, implanting the deep N well in the substrate, removing the mask, and removing the screen oxide layer. Depositing the epitaxial layer can comprise depositing a single crystal silicon over the substrate.

Abstract: According to a disclosed embodiment, a composite MIM capacitor comprises a lower electrode of a lower MIM capacitor situated in a lower interconnect metal layer of a semiconductor die. The composite MIM capacitor further comprises an upper electrode of the lower MIM capacitor situated within a lower interlayer dielectric, where the lower interlayer dielectric separates the lower interconnect metal layer from an upper interconnect metal layer. A lower electrode of the upper MIM capacitor is situated in the upper interconnect metal layer. An upper electrode of the upper MIM capacitor is situated within the upper interlayer dielectric which is, in turn, situated over the upper interconnect metal layer. The upper electrode of the lower MIM capacitor is connected to the lower electrode of the upper MIM capacitor while the lower electrode of the lower MIM capacitor is connected to the upper electrode of the upper MIM capacitor.

Abstract: According to one exemplary embodiment, an integrated circuit chip comprises a first interconnect metal layer. The integrated circuit chip further comprises a first intermediate dielectric layer situated over the first interconnect metal layer. The integrated circuit chip further comprises a metal resistor situated over the first intermetallic dielectric layer and below a second intermetallic dielectric layer. The integrated circuit chip further comprises a second interconnect metal layer over the second intermetallic dielectric layer. The integrated circuit chip further comprises a first intermediate via connected to first terminal of the metal resistor, where the first intermediate via is further connected to a first metal segment patterned in the second interconnect metal layer.

Abstract: A disclosed method for fabricating a structure in a semiconductor die comprises steps of implanting a deep N well in a substrate, depositing an epitaxial layer over the substrate, and forming a P well and a lateral isolation N well over the deep N well, wherein the lateral isolation N well and the P well are fabricated in the substrate and the epitaxial layer, and wherein the lateral isolation N well laterally surrounds the P well, and wherein the deep N well and the lateral isolation N well electrically isolate the P well. Implanting a deep N well can comprise steps of depositing a screen oxide layer over the substrate, forming a mask over the screen oxide layer, implanting the deep N well in the substrate, removing the mask, and removing the screen oxide layer. Depositing the epitaxial layer can comprise depositing a single crystal silicon over the substrate.

Abstract: According to one embodiment, a structure comprises an electrode of a lower MIM capacitor situated in a first interconnect metal layer of a semiconductor die. The structure further comprises a shared electrode of the lower MIM capacitor and an upper MIM capacitor. The structure further comprises an electrode of the upper MIM capacitor situated over the shared electrode. The electrode of the upper MIM capacitor is coupled to the electrode of the lower MIM capacitor through vias and a second interconnect metal layer. In one embodiment, the electrode of the upper MIM capacitor can be divided into two or more segments to allow additional paths for connectivity to reduce the resistance of an electrode of the composite MIM capacitor. In other embodiments, a method for fabricating various embodiments of the composite MIM capacitor is disclosed.

Abstract: According to a disclosed embodiment, a composite MIM capacitor comprises a lower electrode of a lower MIM capacitor situated in a lower interconnect metal layer of a semiconductor die. The composite MIM capacitor further comprises an upper electrode of the lower MIM capacitor situated within a lower interlayer dielectric, where the lower interlayer dielectric separates the lower interconnect metal layer from an upper interconnect metal layer. A lower electrode of the upper MIM capacitor is situated in the upper interconnect metal layer. An upper electrode of the upper MIM capacitor is situated within the upper interlayer dielectric which is, in turn, situated over the upper interconnect metal layer. The upper electrode of the lower MIM capacitor is connected to the lower electrode of the upper MIM capacitor while the lower electrode of the lower MIM capacitor is connected to the upper electrode of the upper MIM capacitor.

Abstract: According to one exemplary embodiment, an integrated circuit chip comprises a first interconnect metal layer. The integrated circuit chip further comprises a first intermediate dielectric layer situated over the first interconnect metal layer. The integrated circuit chip further comprises a metal resistor situated over the first intermetallic dielectric layer and below a second intermetallic dielectric layer. The integrated circuit chip further comprises a second interconnect metal layer over the second intermetallic dielectric layer. The integrated circuit chip further comprises a first intermediate via connected to first terminal of the metal resistor, where the first intermediate via is further connected to a first metal segment patterned in the second interconnect metal layer.

Abstract: According to a disclosed embodiment, an interconnect metal layer is deposited. The interconnect metal layer can be, for example, aluminum, copper, or an aluminum-copper alloy. Then a first dielectric is fabricated over the interconnect metal layer. The first dielectric can be, for example, silicon nitride. A top metal layer is then formed over the first dielectric. The top metal layer can be, for example, titanium nitride. Next, the top metal layer and the first dielectric are patterned and etched to form a capacitor first electrode and a capacitor dielectric. Thereafter a layer of a second dielectric is deposited over the capacitor first electrode and the capacitor dielectric. The second dielectric can be, for example, silicon oxide. Then the second dielectric is etched back, as a result of which spacers covering common sidewalls of the capacitor first electrode and the capacitor dielectric are formed. The spacers protect the capacitor dielectric from being etched during subsequent Processing steps.

Abstract: Structure and method for fabrication of an improved capacitor are disclosed. In one embodiment, the disclosed capacitor includes a metal column comprising a number of interconnect metal segments and a number of via metal segments stacked on one another. The metal column constitutes one electrode of the capacitor. Another electrode of the capacitor is a metal wall surrounding the metal column. In one embodiment, the metal wall is fabricated from a number of interconnect metal structures and a number of via metal structures stacked on one another. In one embodiment, the metal wall is shaped as a hexagon. In this embodiment, a tight packing arrangement is achieved by packing individual hexagonal capacitors “wall to wall” so as to achieve a cluster of individual hexagonal capacitors. The cluster of individual capacitors acts as a single composite capacitor. In one embodiment, the interconnect metal and via metal are both made of copper.

Abstract: An improved thin-film capacitor and methods for forming the same on a surface of a substrate are disclosed. The capacitor includes a bottom conducting plate formed by depositing conductive material within a trench of an insulating layer and planarizing the conducting and insulating layers. A dielectric film is then deposited on the substrate surface, such that at least a portion of the dielectric material remains over the bottom conducting plate. A second conductive layer is then deposited over the surface of the substrate, patterned and etched such that at least a portion of the second conducting material resides over at least a portion of the dielectric material.

Abstract: An improved thin-film capacitor and methods for forming the same on a surface of a substrate are disclosed. The capacitor includes a bottom conducting plate formed by depositing conductive material within a trench of an insulating layer and planarizing the conducting and insulating layers. A dielectric film is then deposited on the substrate surface, such that at least a portion of the dielectric material remains over the bottom conducting plate. A second conductive layer is then deposited over the surface of the substrate, patterned and etched such that at least a portion of the second conducting material resides over at least a portion of the dielectric material.

Abstract: An improved thin-film capacitor and methods for forming the same on a surface of a substrate are disclosed. The capacitor includes a bottom conducting plate formed by depositing conductive material within a trench of an insulating layer and planarizing the conducting and insulating layers. A dielectric film is then deposited on the substrate surface, such that at least a portion of the dielectric material remains over the bottom conducting plate. A second conductive layer is then deposited over the surface of the substrate, patterned and etched such that at least a portion of the second conducting material resides over at least a portion of the dielectric material.