Abstract: A device for determining information of a substance in a matter comprising a substrate layer; an inter-layer dielectric disposed on the substrate layer; an electronic circuitry substantially formed in the inter-layer dielectric and includes a plurality of metal layers with at least one metal layer being used as an inner electrode, a sensing instrument having at least one sensing component that includes a piezoelectric layer and the inner electrode that is positioned adjacent to an inner surface of the piezoelectric layer, and at least one binding layer disposed on the inter-layer dielectric for binding the substance, wherein the sensing component allows the device to determine the information of the substance upon detecting presence of the substance at the binding layer.

Abstract: A device for determining information of a substance in a matter comprising a substrate layer; an inter-layer dielectric disposed on the substrate layer; an electronic circuitry substantially formed in the inter-layer dielectric and includes a plurality of metal layers with at least one metal layer being used as an inner electrode, a sensing instrument having at least one sensing component that includes a piezoelectric layer and the inner electrode that is positioned adjacent to an inner surface of the piezoelectric layer, and at least one binding layer disposed on the inter-layer dielectric for binding the substance, wherein the sensing component allows the device to determine the information of the substance upon detecting presence of the substance at the binding layer.

Abstract: A method for producing a silicon nanosensor integrated with advanced complementary metal oxide semiconductor (CMOS) logic circuit having gate length (Lg) of less than 0.25 ?m, comprising the steps of: allocating a silicon nanosensor region and a CMOS logic circuit region on one bulk silicon substrate; forming silicon nanowires at the allocated nanosensor region while shielding the CMOS logic circuit region; applying a layer of protecting hardmask on the substrate such that the hardmask acts as an extra protection layer to the nanosensor region while acting as a hardmask for CMOS logic circuit formation process thereinafter; subjecting the substrate to selective etching to form trenches, filling the trenches with silicon oxide and subjecting the substrate to chemical mechanical planarization; and removing the hardmask from the substrate in a region-by-region manner, in which the nanosensor region remains unexposed while removing hardmark from the CMOS logic circuit region, and vice versa.

Abstract: An integrated circuit device that includes a substrate as a base of the integrated circuit device, a semiconductor layer disposed on top of the substrate, an isolation layer disposed on top of the semiconductor layer, a plurality of metals disposed above the isolation layer, a transistor including a source and drain region positioned in the semiconductor layer, and a gate electrode connected to the source and drain region and positioned in the isolation layer, wherein the source and drain region, and gate electrode are respectively connected to the metals by electrical contacts, and a Faraday shield positioned laterally between the gate electrode and the drain region in the isolation layer. The Faraday shield is connected to one of the metals through at least one conductive interconnect produced by a damascene process such that the interconnect forms a continuous connection to the metal from the Faraday shield.

Abstract: This disclosure describes a monolithic integrated device that comprises a substrate layer being the base of the device, an inter-layer dielectric disposed on top of the substrate layer and below a passivation layer, an electronic circuitry formed within the inter-layer dielectric and supported by the substrate layer, the electronic circuitry comprises a plurality of metal layers formed by one or more spaced apart metals; and at least one micromachined ultrasonic transducer. Each micromachined ultrasonic transducer comprises a bottom electrode disposed on top of the passivation layer and connected to the electronic circuitry, a piezoelectric disposed on top of the bottom electrode, a top electrode disposed on top of the piezoelectric, and an elastic layer positioned on top of the top electrode. There is a cavity formed below the bottom electrode that extends from the passivation layer to a portion of the inter-layer dielectric.

Abstract: This disclosure describes a monolithic integrated device that comprises a substrate layer being the base of the device, an inter-layer dielectric disposed on top of the substrate layer and below a passivation layer, an electronic circuitry formed within the inter-layer dielectric and supported by the substrate layer, the electronic circuitry comprises a plurality of metal layers formed by one or more spaced apart metals; and at least one micromachined ultrasonic transducer. Each micromachined ultrasonic transducer comprises a bottom electrode disposed on top of the passivation layer and connected to the electronic circuitry, a piezoelectric disposed on top of the bottom electrode, a top electrode disposed on top of the piezoelectric, and an elastic layer positioned on top of the top electrode. There is a cavity formed below the bottom electrode that extends from the passivation layer to a portion of the inter-layer dielectric.

Abstract: Monolithic integrated device having an architecture that allows an acoustic device to transduce either surface acoustic waves or bulk acoustic waves, comprising: a substrate layer being the base of the device; an inter-layer dielectric disposed on top of the substrate layer; an electronic circuitry substantially formed in the inter-layer dielectric and supported by the substrate layer, the electronic circuitry comprises a plurality of metal layers; and a piezoelectric layer being sandwiched between a top electrode and a bottom electrode within the inter-layer dielectric. The top electrode is an upper metal layer belonging to the electronic circuitry and the bottom electrode is a lower metal layer belonging to the electronic circuitry. To transduce the bulk acoustic waves, the inter-layer dielectric is formed with a top cavity above the top electrode and a bottom cavity below the bottom electrode.

Abstract: Monolithic integrated device having an architecture that allows an acoustic device to transduce either surface acoustic waves or bulk acoustic waves, comprising: a substrate layer being the base of the device; an inter-layer dielectric disposed on top of the substrate layer; an electronic circuitry substantially formed in the inter-layer dielectric and supported by the substrate layer, the electronic circuitry comprises a plurality of metal layers; and a piezoelectric layer being sandwiched between a top electrode and a bottom electrode within the inter-layer dielectric. The top electrode is an upper metal layer belonging to the electronic circuitry and the bottom electrode is a lower metal layer belonging to the electronic circuitry. To transduce the bulk acoustic waves, the inter-layer dielectric is formed with a top cavity above the top electrode and a bottom cavity below the bottom electrode.

Abstract: A method for manufacturing a planarized reflective layer disposed on a hinge layer connected to a hinge support post (210) is disclosed. The method comprises depositing a first layer of a first material to form the hinge layer (206), patterning a first mask over the first layer and selectively removing the first material not covered by any of the first mask to form a plurality of recesses, depositing a second layer of a second material over the first layer, patterning a second mask over the second layer and selectively removing the second material not covered by any of the second mask to form a hinge component (212), depositing a reflective layer (202) of a reflective material over the second layer and planarizing the reflective layer (202) to form a substantially planar reflective surface.

Abstract: A method is described for forming capacitors in integrated circuits by making the capacitors concurrently with the fabrication of the interconnection wiring levels. A single additional photolithographic step and two depositions are required to form capacitors within each wiring level. A key feature of the invention is the use of an etch-stop to protect the capacitor dielectric during contact or via etching. The storage plates of the capacitor are formed from two successive conductor levels which can include polysilicon levels as well. The process is particularly suited to the manufacture of logic circuits and can be used effectively in MOSFET, bipolar and BiCMOS processes.