Patents by Inventor Arjun P. Chandran

Arjun P. Chandran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Modified glitch latch for use with power saving dynamic register file structures
    Patent number: 6981169
    Abstract: In the Retirement Payload Array (RPA) of a microprocessor, the signal “READ” is logically combined with the primary clock signal “CLK” in a control circuit of a modified glitch latch such that the glitch latch will only reset, and therefore a reset edge or “glitch” will only appear, when new data is read and the signal IN will return to zero and allow the modified glitch latch to recover.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: December 27, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Arjun P. Chandran, Gregg K. Tsujimoto, Anup S. Mehta
  • Modified retirement payload array
    Patent number: 6870789
    Abstract: In the Retirement Payload Array (RPA) of a microprocessor, the pointer advance signal “ADVANCE POINTER” from the Instruction Retirement Logic (IRL) of the Instruction Scheduling Unit (ISU) is utilized to provide conditional read RPA signals. Consequently, according to the invention, a read of the RPA is completed only if it is determined that the read word line being read in the current cycle is not the same read word line that was read in the previous cycle.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: March 22, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Arjun P. Chandran, Gregg K. Tsujimoto, Anup S. Mehta
  • Modified glitch latch for use with power saving dynamic register file structures
    Publication number: 20030163749
    Abstract: In the Retirement Payload Array (RPA) of a microprocessor, the signal “READ” is logically combined with the primary clock signal “CLK” in a control circuit of a modified glitch latch such that the glitch latch will only reset, and therefore a reset edge or “glitch” will only appear, when new data is read and the signal IN will return to zero and allow the modified glitch latch to recover.
    Type: Application
    Filed: February 26, 2002
    Publication date: August 28, 2003
    Applicant: Sun Microsystems, Inc.
    Inventors: Arjun P. Chandran, Gregg K. Tsujimoto, Anup S. Mehta
  • Power savings in dynamic register file structures
    Publication number: 20030154365
    Abstract: In the Retirement Payload Array (RPA) of a microprocessor, the pointer advance signal “ADVANCE POINTER” from the Instruction Retirement Logic (IRL) of the Instruction Scheduling Unit (ISU) is utilized to provide conditional read RPA signals. Consequently, according to the invention, a read of the RPA is completed only if it is determined that the read word line being read in the current cycle is not the same read word line that was read in the previous cycle.
    Type: Application
    Filed: February 8, 2002
    Publication date: August 14, 2003
    Applicant: Sun Microsystems, Inc.
    Inventors: Arjun P. Chandran, Gregg K. Tsujimoto, Anup S. Mehta