Patents by Inventor Arjun Prabhu

Arjun Prabhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus for generating out-of-order results and out-of-order condition codes in a processor
    Patent number: 6219778
    Abstract: A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results buffer having a number of slots and providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer. Each live instruction in the processor is assigned a slot in the results buffer and the condition code buffer. Each speculative result produced by the execution units is stored in the assigned slot in the results buffer. When an instruction is retired, the results for that instruction are transferred to an architectural result register and any condition codes generated by that instruction are transferred to an architectural condition code register.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: April 17, 2001
    Assignee: Sun Microsystems, Inc.
    Inventors: Ramesh Panwar, Arjun Prabhu
  • Apparatus for precise architectural update in an out-of-order processor
    Patent number: 6085305
    Abstract: A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results buffer having a number of slots and providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer. Each live instruction in the processor is assigned a slot in the results buffer and the condition code buffer. Each speculative result produced by the execution units is stored in the assigned slot in the results buffer. When an instruction is retired, the results for that instruction are transferred to an architectural result register and any condition codes generated by that instruction are transferred to an architectural condition code register.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: July 4, 2000
    Assignee: Sun Microsystems, Inc.
    Inventors: Ramesh Panwar, Arjun Prabhu
  • Method for precise architectural update in an out-of-order processor
    Patent number: 5958047
    Abstract: A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results buffer having a number of slots and providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer. Each live instruction in the processor is assigned a slot in the results buffer and the condition code buffer. Each speculative result produced by the execution units is stored in the assigned slot in the results buffer. When an instruction is retired, the results for that instruction are transferred to an architectural result register and any condition codes generated by that instruction are transferred to an architectural condition code register.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: September 28, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Ramesh Panwar, Arjun Prabhu
  • Computer product for precise architectural update in an out-of-order processor
    Patent number: 5838988
    Abstract: A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results buffer having a number of slots and providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer. Each live instruction in the processor is assigned a slot in the results buffer and the condition code buffer. Each speculative result produced by the execution units is stored in the assigned slot in the results buffer. When an instruction is retired, the results for that instruction are transferred to an architectural result register and any condition codes generated by that instruction are transferred to an architectural condition code register.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: November 17, 1998
    Assignee: Sun Microsystems, Inc.
    Inventors: Ramesh Panwar, Arjun Prabhu