Abstract: Techniques are disclosed relating to handling memory pages for geometry processing in graphics processors. In some embodiments, a set of geometry work includes multiple segments that generate primitive data. The graphics processor may use distributed control circuitry to assign memory pages, from a page pool for a memory, for primitive data from the geometry work and may close memory pages completed by the geometry work. The distributed control circuitry may generate a list of closed pages for a given segment of the set of geometry work. Primary control circuitry may combine multiple lists of closed pages, from the distributed control circuitry, to generate a consolidated list of closed pages for the set of geometry work. This may reduce memory footprint and facilitate traversal of the combined list, in some embodiments.

Abstract: Techniques are disclosed relating to managing page pools for sets of processing work. In some embodiments, page manager circuitry maintains, in memory circuitry, page pool descriptor information that indicates memory pages allocated to multiple different page pools. It may cache page pool descriptor information from the memory circuitry in a page pool descriptor cache, where the page pool descriptor cache includes multiple entries and a given entry is configured to store the following information for a cached page pool descriptor: a location of a corresponding page pool and page pool size information. The page manager circuitry may provide pages to requesting client circuitry from the page pool based on the cached page pool descriptor information.

Abstract: Disclosed techniques relate to parsing and assigning sets of geometry work to distributed hardware slots. In some embodiments, graphics control circuitry implements a plurality of logical slots. Control circuitry may assign a parse version of a set of geometry work to distributed hardware slots of one or more of the graphics processor sub-units that each implement multiple distributed hardware slots. Control circuitry may determine a number of segments for the set of geometry work based on execution of the parse version and assign determined segments to distributed hardware slots of respective graphics processor sub-units for execution. Stitch circuitry may stitch results of the segments processed by the assigned distributed hardware slots.

Abstract: Techniques are disclosed relating to managing page pools for sets of processing work. In some embodiments, a processor assigns sets of processing work to respective primary slots. Page manager circuitry may maintain, in a memory, page pool descriptor information for memory pages allocated to multiple different page pools, maintain a mapping of multiple primary slots of the processor circuitry to a first page pool of the page pools, and cache page pool descriptor entries in the page pool descriptor cache. The page manager circuitry may provide pages to requesting client circuitry from the first page pool for the multiple mapped primary slots. In some embodiments, the page manager circuitry pre-fetches virtual pages. The page manager circuitry may include primary and distribute components.

Abstract: Techniques are disclosed relating to updating page pools in the context of cached page pool descriptors. In some embodiments, a processor is configured to assign a set of processing work to a first page pool of memory pages. Page manager circuitry may cache page pool descriptor entries in cache circuitry, where a given page pool descriptor entry indicates a set of pages assigned to a page pool. In response to a determination to grow the first page pool, the processor may communicate a grow list to the page manager circuitry, that identifies a set of memory blocks from the memory to be added to the first page pool. The page manager circuitry may then update a cached page pool descriptor entry for the first page pool to indicate the added memory blocks and generate a signal to inform the processor that the cached page pool descriptor entry is updated.