Abstract: A WLP device is provided with a flange shaped UBM or an embedded partial solder ball UBM on top of a copper post style circuit connection.

Abstract: Wafer-level package (semiconductor) devices are described that have a pillar structure that extends at least partially into a solder bump to mitigate thermal stresses to the solder bump. In implementations, the wafer-level package device may comprise an integrated circuit chip having a surface and a solder bump disposed over the surface. The wafer-level package device may also include a pillar structure disposed over the surface that extends at least partially into the solder bump.

Abstract: Semiconductor devices are described that have an extended under ball metallization configured to mitigate dielectric layer cracking due to stress, particularly stress caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests, or cyclic bending tests, and so on. In an implementation, the semiconductor package devices include an integrated circuit chip having a solder ball and under ball metallization, formed on the integrated circuit chip, which is configured to receive the solder ball so that the solder ball and the under ball metallization have a contact area there between, wherein the area of the under ball metallization is area greater than the contact area.

Abstract: Embodiments provide methods for etching and depositing silicon materials on a substrate. In one example, the method includes heating a substrate containing a silicon-containing material to a temperature of about 800° C. or less and removing a portion of the silicon-containing material and a contaminant to reveal an exposed surface of the silicon-containing material during an etching process and depositing a silicon-containing layer on the exposed surface of the silicon-containing material during a deposition process. The method further provides conducting the etching and deposition processes in the same chamber and utilizing chlorine gas and a silicon source gas during the etching and deposition processes. In some examples, the silicon-containing material is removed at a rate within a range from about 2 ? per minute to about 20 ? per minute during the etching process.

Abstract: A WLP device is provided with a flange shaped UBM or an embedded partial solder ball UBM on top of a copper post style circuit connection.

Abstract: A WLP device is provided with a flange shaped UBM or an embedded partial solder ball UBM on top of a copper post style circuit connection.

Abstract: An enhanced redistribution layer is provided that geometrically expands redistribution layer (RDL) pads associated with a ball grid array of a wafer level package (WLP) to provide tensile stress relief during temperature cycle and/or drop testing of the WLP.

Abstract: A heat dissipating wafer level package and method for manufacturing a heat dissipating wafer level package is provided. The heat dissipating wafer level package has a thermally conductive coating integrated thereon which facilitates the dissipation of heat from a device into the surrounding air and/or the thermal transfer of heat away from the device toward a heat spreader or heat sink. Additionally, the coating enhances the structural integrity and strength of the wafer during the manufacturing process as well as the resulting WLP.

Abstract: A WLP device is provided with a flange shaped UBM or an embedded partial solder ball UBM on top of a copper post style circuit connection.

Abstract: An enhanced redistribution layer is provided that geometrically expands redistribution layer (RDL) pads associated with a ball grid array of a wafer level package (WLP) to provide tensile stress relief during temperature cycle and/or drop testing of the WLP.

Abstract: An enhanced redistribution layer is provided that geometrically expands redistribution layer (RDL) pads associated with a ball grid array of a wafer level package (WLP) to provide tensile stress relief during temperature cycle and/or drop testing of the WLP.

Abstract: A method for processing a substrate including a pre-cleaning etch and reduced pressure process is disclosed. The pre-cleaning process involves introducing a substrate into a processing chamber; flowing an etching gas into the processing chamber; processing at least a portion of the substrate with the etching gas to remove a contaminated or damaged layer from a substrate surface; stopping flow of the etching gas; evacuating the processing chamber to achieve a reduced pressure in the chamber; and processing the substrate surface at the reduced pressure. Epitaxial deposition is then used to form an epitaxial layer on the substrate surface.

Abstract: A method for processing a substrate including a pre-cleaning etch and reduced pressure process is disclosed. The pre-cleaning process involves introducing a substrate into a processing chamber; flowing an etching gas into the processing chamber; processing at least a portion of the substrate with the etching gas to remove a contaminated or damaged layer from a substrate surface; stopping flow of the etching gas; evacuating the processing chamber to achieve a reduced pressure in the chamber; and processing the substrate surface at the reduced pressure. Epitaxial deposition is then used to form an epitaxial layer on the substrate surface.

Abstract: The present invention provides systems and methods of forming an epitaxial film on a substrate. After heating in a process chamber, the substrate is exposed to a silicon source and at least one of SiH2(CH3)2, SiH(CH3)3, Si(CH3)4, 1,3-disilabutane, and C2H2, at a temperature of greater than about 250 degrees Celsius and a pressure greater than about 1 Torr so as to form an epitaxial film on at least a portion of the substrate. Then, the substrate is exposed to an etchant so as to etch the epitaxial film and any other films formed during the deposition. The deposition and etching may be repeated until a film of a desired thickness is achieved. Numerous other aspects are disclosed.

Abstract: Systems, methods, and apparatus are provided for using a cluster tool to pre-clean a substrate in a first processing chamber utilizing a first gas prior to epitaxial film formation, transfer the substrate from the first processing chamber to a second processing chamber through a transfer chamber under a vacuum, and form an epitaxial layer on the substrate in the second processing chamber without utilizing the first gas. Numerous additional aspects are disclosed.

Abstract: The present invention provides methods, systems, and apparatus for epitaxial film formation that includes an epitaxial chamber adapted to form an epitaxial layer on a substrate; a deposition gas manifold adapted to supply at least one deposition gas and a carrier gas to the epitaxial chamber; and an etchant gas manifold, separate from the deposition gas manifold, and adapted to supply at least one etchant gas and a carrier gas to the epitaxial chamber. Numerous other aspects are disclosed.

Abstract: Embodiments provide a method for etching or smoothing a silicon material on a substrate. In one example, the method provides positioning a substrate containing a contaminant disposed on a silicon material within a process chamber, heating the substrate to a temperature of less than 800° C., and exposing the silicon material to an etching gas that contains a chlorine-containing gas and a silicon source gas. The contaminant and a predetermined thickness of the silicon material are removed during the etching process. In another example, the method provides that the substrate contains a first silicon surface having a surface roughness of about 1 nm RMS or greater, exposing the substrate to the etching gas to form a second silicon surface from the first silicon surface during a smoothing process, wherein the second silicon surface has a surface roughness of less than 1 nm RMS.

Abstract: In one example, a method of epitaxially forming a silicon-containing material on a substrate surface is presented which includes positioning a substrate into a process chamber. The substrate has a monocrystalline surface and at least a second surface, such as an amorphous surface and/or a polycrystalline surface. The substrate is exposed to a deposition gas to deposit an epitaxial layer on the monocrystalline surface and a polycrystalline layer on the second surface. The deposition gas preferably contains a silicon source and at least a second elemental source, such as a germanium source, a carbon source and/or combinations thereof. Thereafter, the method further provides exposing the substrate to an etchant gas to etch the polycrystalline layer and the epitaxial layer in a manner such that the polycrystalline layer is etched at a faster rate than the epitaxial layer.

Abstract: Aspects of the invention generally provide an apparatus and method for processing substrates using a multi-chamber processing system that is adapted to process substrates and analyze the results of the processes performed on the substrate. In one aspect of the invention, one or more analysis steps and/or pre-processing steps are performed on the substrate to provide data for processes performed on subsequent substrates. In one aspect of the invention, a system controller and one or more analysis devices are utilized to monitor and control a process chamber recipe and/or a process sequence to reduce substrate scrap due to defects in the formed device and device performance variability issues. Embodiments of the present invention also generally provide methods and a system for repeatably and reliably forming semiconductor devices used in a variety of applications.

Abstract: Aspects of the invention generally provide an apparatus and method for processing substrates using a multi-chamber processing system that is adapted to process substrates and analyze the results of the processes performed on the substrate. In one aspect of the invention, one or more analysis steps and/or precleaning steps are utilized to reduce the effect of queue time on device yield. In one aspect of the invention, a system controller and the one or more analysis chambers are utilized to monitor and control a process chamber recipe and/or a process sequence to reduce substrate scrap due to defects in the formed device and device performance variability issues. Embodiments of the present invention also generally provide methods and a system for repeatably and reliably forming semiconductor devices used in a variety of applications.