Patents by Inventor Arkadiy Morgenshtein

Arkadiy Morgenshtein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180090290
    Abstract: An on/off switching circuit includes an on/off switch switchable between an on state and an off state, an light emitting diode (LED) driver to power one or more LEDs to illuminate an area of interest, a switch control unit to transition the on/off switch between the on and off states, the switch control unit including a light sensing circuit comprising at least one LED of the LEDs as a light sensor, and a bi-directional gate circuit. When the on/off switch is in the off state the bi-directional gate is in a first conducting state in which the bi-directional gate circuit connects the light sensor to the light sensing circuit, and when the on/off switch is in the on state the bi-directional gate is in a second conducting state in which the bi-directional gate connects the LED driver to the one or more LEDs including the light sensor.
    Type: Application
    Filed: September 20, 2017
    Publication date: March 29, 2018
    Applicant: GIVEN IMAGING LTD.
    Inventor: Arkadiy Morgenshtein
  • Patent number: 9411699
    Abstract: A computer program product for provision of prioritization metrics for post-Si failure localization is provided. The computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and executable by a processing circuit to cause the processing circuit to, receive an output of a failure localization tool applied to hardware verification debug processing, recognize, from the output, numbers of mis-compared resources to which each instruction of the failure localization tool is related, apply a priority gradient to each instruction based on the corresponding numbers of the mis-compared resources and conduct further debug processing with respect to each instruction in accordance with the applied priority gradient.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: August 9, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Arkadiy Morgenshtein
  • Publication number: 20120194219
    Abstract: A complementary logic circuit contains first and second logic inputs, first and second dedicated logic terminals, a high-voltage terminal configured for connection to a high constant voltage, a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor and an n-type transistor. The p-type transistor and n-type transistor each have a respective outer diffusion connection, gate connection, inner diffusion connection, and bulk connection. The first and second dedicated logic terminals are connected respectively to the outer diffusion connection of the p-type transistor and the outer diffusion connection of the n-type transistor. The inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor are connected together to form a common diffusion logic terminal.
    Type: Application
    Filed: April 5, 2012
    Publication date: August 2, 2012
    Applicant: Technion Research & Development Foundation Ltd.
    Inventors: Alexander FISH, Arkadiy Morgenshtein
  • Patent number: 8225265
    Abstract: A method for modifying a logic circuit layout to optimize circuit propagation delays for improved circuit operation is presented. The layout includes multiple logic gates connected by conductive segments. An initial layout of a physical electronic logic circuit having the plurality of logic gates is input. A respective size is determined for each of the logic gates in accordance with the initial layout and a circuit propagation delay criterion. The circuit propagation delay criterion is a joint function of properties of at least some of the logic gates and at least some of the conductive segments. A modified logic circuit layout is output. The modified logic circuit layout includes a layout of the logic gates arranged in accordance with the initial layout, where each of the logic gates is modified according to the respective determined size, thereby to obtain a modification of the logic circuit layout incorporating an optimized circuit propagation delay.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: July 17, 2012
    Assignee: Technion Research & Development Foundation Ltd.
    Inventors: Arkadiy Morgenshtein, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman
  • Patent number: 8188767
    Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor, and an n-type transistor. The p-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The n-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: May 29, 2012
    Assignee: Technion Research & Development Foundation Ltd.
    Inventors: Alexander Fish, Arkadiy Morgenshtein
  • Publication number: 20120126853
    Abstract: A complementary logic circuit, comprising: a first and second logic input; a first and second dedicated logic terminal; a p-type transistor network comprising multiple p-type transistors, for implementing a predetermined logic function, and having an outer diffusion connection connected to the first dedicated logic terminal, a first network gate connection connected to the first logic input, and an inner diffusion connection; and an n-type transistor network comprising multiple n-type transistors, for implementing a logic function complementary to the predetermined logic function, and having an outer diffusion connection connected to the second dedicated logic terminal, a first network gate connection connected to the second logic input, and an inner diffusion connection; the inner diffusion connections of the p-type transistor network and of the n-type transistor network being connected to form a common diffusion logic terminal.
    Type: Application
    Filed: February 2, 2012
    Publication date: May 24, 2012
    Applicant: Technion Research & Development Foundation Ltd.
    Inventors: Arkadiy MORGENSHTEIN, Alexander Fish, Israel A. Wagner
  • Patent number: 8161427
    Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: April 17, 2012
    Assignee: Technion Research & Development Foundation Ltd.
    Inventors: Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner
  • Publication number: 20120005639
    Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor, and an n-type transistor. The p-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The n-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 5, 2012
    Applicant: Technion Research & Development Foundation Ltd.
    Inventors: Alexander Fish, Arkadíy Morgenshtein
  • Patent number: 8004316
    Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor, and an n-type transistor. The p-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The n-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: August 23, 2011
    Assignee: Technion Research & Development Foundation Ltd.
    Inventors: Alexander Fish, Arkadiy Morgenshtein
  • Patent number: 7799205
    Abstract: An ion concentration sensor produces a signal reflective of the ion concentration within a solution. The ion concentration sensor is based on an ion sensitive transistor having a solution input, a reference input, a diffusion input, and a diffusion output. The ion sensitive transistor is connected as a pass transistor, such that the diffusion output provides an electrical signal indicating an ion concentration in a solution contacting the solution input.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: September 21, 2010
    Assignee: Technion Research & Development Foundation Ltd.
    Inventors: Arkadiy Morgenshtein, Uri Dinnar, Yael Nemirovsky
  • Publication number: 20100231263
    Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor, and an n-type transistor. The p-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The n-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection.
    Type: Application
    Filed: February 1, 2006
    Publication date: September 16, 2010
    Inventors: Alexander Fish, Arkadiy Morgenshtein
  • Publication number: 20100194439
    Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection.
    Type: Application
    Filed: April 12, 2010
    Publication date: August 5, 2010
    Applicant: Technion Research & Development Foundation Ltd.
    Inventors: Arkadiy MORGENSHTEIN, Alexander Fish, Israel A. Wagner
  • Patent number: 7716625
    Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: May 11, 2010
    Assignee: Technion Research & Development Foundation Ltd.
    Inventors: Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner
  • Patent number: 7659751
    Abstract: A method of designing logic circuit provides a logic circuit which includes a first transistor network and a complementary second transistor network connected at a central node. The central node serves as a first logic output. Each of the transistor networks is also connected to a respective root. A third transistor network is connected between an intermediate node of one of the transistor networks and the network's respective root. The third transistor network has a complementary structure to the transistors between the intermediate node and the central node, and includes a logic output The third transistor network (the graft network) provides a second logic output to the logic circuit.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: February 9, 2010
    Assignee: Technion Research & Development Foundation Ltd.
    Inventor: Arkadiy Morgenshtein
  • Publication number: 20090294653
    Abstract: An ion concentration sensor produces a signal reflective of the ion concentration within a solution. The ion concentration sensor is based on an ion sensitive transistor having a solution input, a reference input, a diffusion input, and a diffusion output. The ion sensitive transistor is connected as a pass transistor, such that the diffusion output provides an electrical signal indicating an ion concentration in a solution contacting the solution input.
    Type: Application
    Filed: June 2, 2009
    Publication date: December 3, 2009
    Applicant: Technion Research & Development Foundation Ltd.
    Inventors: Arkadiy MORGENSHTEIN, Uri DINNAR, Yael NEMIROVSKY
  • Publication number: 20090150847
    Abstract: A method for modifying a logic circuit layout to optimize circuit propagation delays for improved circuit operation is presented. The layout includes multiple logic gates connected by conductive segments. An initial layout of a physical electronic logic circuit having the plurality of logic gates is input. A respective size is determined for each of the logic gates in accordance with the initial layout and a circuit propagation delay criterion. The circuit propagation delay criterion is a joint function of properties of at least some of the logic gates and at least some of the conductive segments. A modified logic circuit layout is output. The modified logic circuit layout includes a layout of the logic gates arranged in accordance with the initial layout, where each of the logic gates is modified according to the respective determined size, thereby to obtain a modification of the logic circuit layout incorporating an optimized circuit propagation delay.
    Type: Application
    Filed: December 1, 2008
    Publication date: June 11, 2009
    Applicant: Technion Research & Development Foundation Ltd.
    Inventors: Arkadiy Morgenshtein, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman
  • Patent number: 7544979
    Abstract: An ion concentration sensor produces a signal reflective of the ion concentration within a solution. The ion concentration sensor is based on an ion sensitive transistor having a solution input, a reference input, a diffusion input, and a diffusion output. The ion sensitive transistor is connected as a pass transistor, such that the diffusion output provides an electrical signal indicating an ion concentration in a solution contacting the solution input.
    Type: Grant
    Filed: April 16, 2004
    Date of Patent: June 9, 2009
    Assignee: Technion Research & Development Foundation Ltd.
    Inventors: Arkadiy Morgenshtein, Uri Dinnar, Yael Nemirovsky
  • Publication number: 20080106303
    Abstract: A logic circuit consists of a first transistor network and a complementary second transistor network connected at a central node. The central node serves as a first logic output. Each of the transistor networks is also connected to a respective root. A third transistor network is connected between an intermediate node of one of the transistor networks and the network's respective root. For a nonhomogeneous graft, the third transistor network has a complementary structure to the transistors between the intermediate node and the central node, is of the opposite transistor type as the given transistor network, and has equivalent inputs relative to the transistors between the intermediate node and the central node.
    Type: Application
    Filed: December 27, 2007
    Publication date: May 8, 2008
    Applicant: Technion Research & Development Foundation Ltd.
    Inventor: Arkadiy Morgenshtein
  • Patent number: 7345511
    Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: March 18, 2008
    Assignee: Technion Research & Development Foundation Ltd.
    Inventors: Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner
  • Patent number: 7336104
    Abstract: A logic circuit consists of a first transistor network and a complementary second transistor network connected at a central node. The central node serves as a first logic output. Each of the transistor networks is also connected to a respective root. A third transistor network is connected between an intermediate node of one of the transistor networks and the network's respective root. For a homogeneous graft, the third transistor network has a complementary structure to the transistors between the intermediate node and the central node, is of the same transistor type as the given transistor network, and has inverted inputs relative to the transistors between the intermediate node and the central node. The third transistor network (the graft network) provides a second logic output to the logic circuit.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: February 26, 2008
    Assignee: Technion Research & Development Foundation Ltd.
    Inventor: Arkadiy Morgenshtein