Abstract: The present disclosure provides a new wet atomic layer etch (ALE) process for etching copper. More specifically, the present disclosure provides various embodiments of methods that utilize new etch chemistries for etching copper in a wet ALE process. By utilizing the new etch chemistries disclosed herein within a wet ALE process, the present disclosure provides a highly selective etch of copper with monolayer precision.

Abstract: The present disclosure provides a new wet atomic layer etch (ALE) process for etching copper. More specifically, the present disclosure provides various embodiments of methods that utilize new etch chemistries for etching copper in a wet ALE process. By utilizing the new etch chemistries disclosed herein within a wet ALE process, the present disclosure provides a highly selective etch of copper with monolayer precision.

Abstract: A method of etching a metal includes performing at least two cycles of an etch process. A cycle of the etch process includes: performing a surface modification on an exposed surface of a metal layer over a substrate, performing a hydrogen treatment on the metal layer, and performing a cleaning treatment on the metal layer. The hydrogen treatment forms a layer of reaction products on the metal layer. The cleaning treatment removes the layer of reaction products.

Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry and a first bonding layer. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over the active circuitry and a second bonding layer on the obstructive material. The second bonding layer can be directly bonded to the first bonding layer without an adhesive. The obstructive material can be configured to obstruct external access to the active circuitry.

Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry and a first bonding layer. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over the active circuitry and a second bonding layer on the obstructive material. The second bonding layer can be directly bonded to the first bonding layer without an adhesive. The obstructive material can be configured to obstruct external access to the active circuitry.

Abstract: A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

Abstract: A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

Abstract: An assembly with modules (110, 1310) containing integrated circuits and attached to a wiring substrate (120) is reinforced by one or more reinforcement frames (410) attached to the wiring substrate. The modules are located in openings (e.g. cavities and/or through-holes 414) in the reinforcement frame. Other features are also provided.

Abstract: A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

Abstract: An assembly with modules (110, 1310) containing integrated circuits and attached to a wiring substrate (120) is reinforced by one or more reinforcement frames (410) attached to the wiring substrate. The modules are located in openings (e.g. cavities and/or through-holes 414) in the reinforcement frame. Other features are also provided.

Abstract: A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

Abstract: An assembly with modules (110, 1310) containing integrated circuits and attached to a wiring substrate (120) is reinforced by one or more reinforcement frames (410) attached to the wiring substrate. The modules are located in openings (e.g. cavities and/or through-holes 414) in the reinforcement frame. Other features are also provided.

Abstract: A first semiconductor chip is formed using a first process technology. A plurality of through-vias are formed in the first semiconductor chip and the first semiconductor chip is thinned such that each through-via extends from the upper surface to the lower surface of the chip. A second semiconductor chip is formed using a second process technology that is different than the first process technology. The second semiconductor chip has a plurality of contacts at a surface. The first semiconductor chip is mounted adjacent the semiconductor chip such that ones of the through-vias are electrically coupled to associated ones of the contacts.

Abstract: A semiconductor device includes a semiconductor substrate having an upper surface and a lower surface opposed to the upper surface. Integrated circuitry is formed at the upper surface of the semiconductor substrate. A plurality of active through-vias are electrically coupled to the integrated circuitry and extend from the upper surface to the lower surface of the semiconductor substrate. In addition, a plurality of other through-vias extend from the upper surface to the lower surface of the semiconductor substrate and are electrically isolated from any integrated circuitry in the substrate.

Abstract: An electronic component includes a first component and a second component, each having a surface that includes a plurality of exposed contacts separated by an insulating material. A sandwich layer is disposed between the surface of the first component and the surface of the second component. The surface of the first component is then attached to the surface of the second component with the sandwich layer therebetween. The sandwich layer forms conductive areas between contacts of the first component and contacts of the second component and forms an insulator between the conductive areas.

Abstract: A configuration of resistive memory cells is disclosed. In one embodiment, the configuration of resistive memory cells comprises a plurality of first current lines; a plurality of second current lines; and a plurality of third current lines.

Abstract: A configuration of resistive memory cells is disclosed. In one embodiment, the configuration of resistive memory cells comprises a plurality of first current lines; a plurality of second current lines; and a plurality of third current lines.

Abstract: A continuous contact hole is formed in an insulation layer that separates a storage capacitor from a switching transistor. All except a section of the contact hole is filled with poly-Si. A conductive, oxidizable interlayer and a conductive oxygen barrier layer are deposited on the Poly-Si in the remaining section of the contact hole such that the interlayer is completely surrounded by the poly-Si of the contact hole, the insulation layer, and the barrier layer.

Abstract: A storage capacitor, in particular a ferroelectric or paraelectric storage capacitor, and an associated contact-making structure are formed in such a way that the storage capacitor has a first electrode layer, a second electrode layer and a dielectric, ferroelectric or paraelectric capacitor intermediate layer. Proceeding from the plane of the surface of the insulation layer, the storage capacitor extends at least partly into the interior of the via contact and is electrically connected to the via contact.

Abstract: A method for fabricating a memory cell, in particular, a DRAM memory cell, having a transistor and a trench capacitor that are connected to one another through a buried strap contact includes applying at least one diffusion barrier on an upper surface of a first filling material of the trench capacitor to prevent an undesirable outdiffusion of dopant from the first filling material. Thus, with the diffusion barrier intact, at most a dopant that is possibly present in a second filling material can outdiffuse into adjoining regions. However, the outdiffusion of dopant from the first filling material can be initiated in a targeted manner by breaking open the diffusion barrier by a thermal treatment. Through the possibility of restraining the diffusion of the dopant until a suitable point in the process, it is possible to avoid an excessive outdiffusion into a contact region with a transistor.