Abstract: A method for making a semiconductor device can include picking and placing a top die onto a bottom die on a wafer such that a first set of operational contacts of the bottom die are aligned with and physically contacting a second set of operational contacts of the top die, and such that a first set of test contacts are exposed and not fully covered by the top die, and annealing the wafer to induce bonding of the second set of operational contacts of the top die with the first set of operational contacts of the bottom die in a plasma-equipped furnace chamber while exciting a plasma along with flowing gas including nitrogen and hydrogen to hinder oxidation of metal, such as copper, in the first set of test contacts during the annealing.

Abstract: A method includes forming a first die in a first wafer. The first die includes first bond pads and one or more first test pads on a first side of the first die and a first capping layer over each of the one or more first test pads. The method further includes contacting at least one first capping layer with one or more first test probes to perform a first test, identifying the first die as a known good die based on a result of the first test, and removing at least a portion of each first capping layer.

Abstract: A method for fabricating semiconductor devices is disclosed. The method includes forming a stack on a first substrate. A laser liftoff layer is interposed between the stack and the first substrate. The method includes forming a plurality of first interconnect structures over a first side of the stack. The method includes attaching a second substrate to the stack on the first side, with the plurality of first interconnect structures interposed between the stack and the second substrate; removing the first substrate by applying radiation on the laser liftoff layer. The method includes forming a plurality of second interconnect structures on a second side of the stack opposite to the first side.

Abstract: A method of etching a metal includes performing at least two cycles of an etch process. A cycle of the etch process includes: performing a surface modification on an exposed surface of a metal layer over a substrate, performing a hydrogen treatment on the metal layer, and performing a cleaning treatment on the metal layer. The hydrogen treatment forms a layer of reaction products on the metal layer. The cleaning treatment removes the layer of reaction products.

Abstract: A method of integrating a semiconductor device with periphery circuit including connecting the semiconductor device to a periphery circuit that includes forming a vertical DRAM cell on a substrate, flipping the vertical DRAM cell, grinding and removing the substrate to expose a first epitaxial layer, forming a first wafer embedded with a first bonding pad on a hard mask that is deposited on a plurality of bit lines, flipping the vertical DRAM cell back, forming a second wafer embedded with a second bonding pad that is formed on an insulating layer, connecting the insulating layer to the periphery circuit through a second contact that is embedded in the insulating layer, bonding the first wafer and the second wafer by hybrid bonding, and forming back end of lines on top of the DRAM cell.

Abstract: A method includes providing a first substrate having a first bonding surface. The method includes providing a second substrate having a second bonding surface. The method includes coupling a metal-containing precursor to the first bonding surface and the second bonding surface. The method includes activating the metal-containing precursor on the first bonding surface and the second bonding surface. The method further includes chemically reacting the activated metal-containing precursor on the first bonding surface and the second bonding surface to form an interface between the first substrate and the second substrate.

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The method includes forming a first device structure on a first substrate, a first laser liftoff layer on the first device structure, a protective layer on the first laser liftoff layer, and a second substrate on the protective layer. The method includes de-attaching, through applying radiation on the first laser liftoff layer, the protective layer from the first laser liftoff layer, with a first surface of the second substrate remaining in contact with a second surface of the protective layer. The protective layer is transparent to the radiation.

Abstract: A method of processing a substrate that includes: forming an infrared (IR) absorbing separation layer over a first substrate; forming one or more layers over the IR absorbing separation layer; bonding the first substrate and a second substrate at a bonding interface between the one or more layers and the second substrate using a direct bonding technique to form a wafer stack; exposing the wafer stack to an infrared (IR) light irradiation to separate the first substrate from the one or more layers.

Abstract: A hybrid bonding apparatus includes a hybrid bonder that has a bonder head and is configured to bond a first semiconductor structure to a second semiconductor structure via hybrid bonding. The hybrid bonding apparatus also includes an X-ray probe having an X-ray source and a detector. The bonder head is positioned in a measurement gap between the X-ray source and the detector or positioned in a measurement space opposite to both the X-ray source and the detector. The X-ray probe is configured to irradiate X-rays through the first semiconductor structure and the second semiconductor structure, in whole or in part, to measure relative positions of the first semiconductor structure and the second semiconductor structure. The hybrid bonder is configured to align the first semiconductor structure and the second semiconductor structure based on the relative positions of the first semiconductor structure and the second semiconductor structure.

Abstract: A method for fabricating semiconductor devices is disclosed. The method includes forming a stack on a first substrate. A laser liftoff layer is interposed between the stack and the first substrate. The method includes forming a plurality of first interconnect structures over a first side of the stack. The method includes attaching a second substrate to the stack on the first side, with the plurality of first interconnect structures interposed between the stack and the second substrate; removing the first substrate by applying radiation on the laser liftoff layer. The method includes forming a plurality of second interconnect structures on a second side of the stack opposite to the first side.

Abstract: In some implementations, a method may include providing a silicon on insulator (SOI) substrate having a first semiconductor layer, a buried oxide layer over the first semiconductor region, and a second semiconductor region over the buried oxide, the second semiconductor region having a plurality of recesses exposing the underlying buried oxide, each recess having a shape and size configured to accommodate a die. In addition, the device may include bonding a plurality of semiconductor dies to the buried oxide through the plurality of recesses.

Abstract: The present disclosure provides a new wet atomic layer etch (ALE) process for etching copper. More specifically, the present disclosure provides various embodiments of methods that utilize new etch chemistries for etching copper in a wet ALE process. By utilizing the new etch chemistries disclosed herein within a wet ALE process, the present disclosure provides a highly selective etch of copper with monolayer precision.

Abstract: The present disclosure provides a new wet atomic layer etch (ALE) process for etching copper. More specifically, the present disclosure provides various embodiments of methods that utilize new etch chemistries for etching copper in a wet ALE process. By utilizing the new etch chemistries disclosed herein within a wet ALE process, the present disclosure provides a highly selective etch of copper with monolayer precision.

Abstract: A method of etching a metal includes performing at least two cycles of an etch process. A cycle of the etch process includes: performing a surface modification on an exposed surface of a metal layer over a substrate, performing a hydrogen treatment on the metal layer, and performing a cleaning treatment on the metal layer. The hydrogen treatment forms a layer of reaction products on the metal layer. The cleaning treatment removes the layer of reaction products.

Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry and a first bonding layer. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over the active circuitry and a second bonding layer on the obstructive material. The second bonding layer can be directly bonded to the first bonding layer without an adhesive. The obstructive material can be configured to obstruct external access to the active circuitry.

Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry and a first bonding layer. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over the active circuitry and a second bonding layer on the obstructive material. The second bonding layer can be directly bonded to the first bonding layer without an adhesive. The obstructive material can be configured to obstruct external access to the active circuitry.

Abstract: A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

Abstract: A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

Abstract: An assembly with modules (110, 1310) containing integrated circuits and attached to a wiring substrate (120) is reinforced by one or more reinforcement frames (410) attached to the wiring substrate. The modules are located in openings (e.g. cavities and/or through-holes 414) in the reinforcement frame. Other features are also provided.

Abstract: A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.