Patents by Inventor Arlette Marty-Blavier

Arlette Marty-Blavier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data communication system and method
    Patent number: 8307227
    Abstract: A data communication system includes one or more data processing units and includes a central control unit. The decentralized data processing units are connected to the central control unit by data connection. The central control unit includes a synchronisation unit for outputting via the data connection an synchronisation signal to the data processing unit. The data processing unit includes a data generator for generating data and transmitting, after the synchronisation signal, data to the central control unit.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: November 6, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Philippe Lance, Arlette Marty-Blavier
  • Regulated voltage system and method of protection therefor
    Patent number: 8237424
    Abstract: A system comprises a voltage regulator operably coupled to an external component, a voltage regulator reset circuit and at least one functional element supplied with a voltage by the voltage regulator. The voltage regulator reset circuit is arranged to repetitively reset the voltage regulator upon disconnection of the external component.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: August 7, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Arlette Marty-Blavier, Philippe Lance, Stephan Ollitrault, Yean Ling Teo
  • REGULATED VOLTAGE SYSTEM AND METHOD OF PROTECTION THEREFOR
    Publication number: 20100283444
    Abstract: A system comprises a voltage regulator operably coupled to an external component, a voltage regulator reset circuit and at least one functional element supplied with a voltage by the voltage regulator. The voltage regulator reset circuit is arranged to repetitively reset the voltage regulator upon disconnection of the external component.
    Type: Application
    Filed: January 18, 2006
    Publication date: November 11, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Arlette Marty-Blavier, Philippe Lance, Stephan Ollitrault, Yean Ling Teo
  • DATA COMMUNICATION SYSTEM AND METHOD
    Publication number: 20100004828
    Abstract: A data communication system includes one or more data processing units and includes a central control unit. The decentralized data processing units are connected to the central control unit by data connection. The central control unit (10) includes a synchronisation unit for outputting via the data connection an synchronisation signal to the data processing unit. The data processing unit includes a data generator for generating data and transmitting, after the synchronisation signal, data to the central control unit.
    Type: Application
    Filed: November 8, 2006
    Publication date: January 7, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Philippe Lance, Arlette Marty-Blavier
  • DATA COMMUNICATION SYSTEM AND METHOD
    Publication number: 20090313407
    Abstract: A data communication system includes one or more data processing units and includes a central control unit. The decentralized data processing units are connected to the central control unit by data connection. The central control unit includes a synchronisation unit for outputting via the data connection an electric synchronisation signal to the data processing unit. The data processing unit includes a data generator for generating data and transmitting, after the electric synchronisation signal, data to the central control unit. The central control unit further includes a discharge signal generator for outputting a discharge signal via the data connection to the data processing unit.
    Type: Application
    Filed: August 1, 2006
    Publication date: December 17, 2009
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Philippe Lance, Arlette Marty-Blavier, Eric Rolland
  • Method of manufacturing BICMOS integrated circuits
    Patent number: 5691226
    Abstract: A method of manufacturing both bipolar and CMOS devices including vertical PNP, NPN, PMOS and NMOS devices on the same chip, includes the steps of, simultaneously forming an N+ region (14) on part of a P base region (11) of the vertical NPN device to form the emitter contact region thereof, an N+ region (14) on a part of an N- epitaxial layer (5) of the vertical NPN device to form the collector contact region thereof, N+ regions (14) on first and second parts of a P well region (8) of the NMOS device to form the source and drain thereof, and an N+ region (14) on an N base region (9) of the vertical PNP device to form the base contact thereof.
    Type: Grant
    Filed: June 25, 1996
    Date of Patent: November 25, 1997
    Assignee: Motorola, Inc.
    Inventors: Juergen Foerstner, Myriam Combes, Arlette Marty-Blavier, Guy Hautekiet
  • Method of making BiCMOS circuit
    Patent number: 5691224
    Abstract: A method of manufacturing an integrated circuit having a buried layer of a low doped type of conductivity (2) and a buried layer of a highly doped type of the same conductivity (3) by masking a substrate (1) so as to define open areas on the substrate where it is desired to provide the two buried layers and doping the open areas of the substrate with a low concentration of dopants to form the low doped type of buried layer (2) is formed. Then one open area where the low doped type of buried layer (2) is formed is masked and the other open area is doped with a high concentration of dopants to form the highly doped type of buried layer (3).
    Type: Grant
    Filed: June 25, 1996
    Date of Patent: November 25, 1997
    Assignee: Motorola, Inc.
    Inventors: Juergen Foerstner, Myriam Combes, Arlette Marty-Blavier, Guy Hautekiet