Abstract: A method and apparatus for converting between analog signals and corresponding digital signals that is accurate relative to the actual value of the input signal, and not relative to the upper limit on the analog input signal. The method and apparatus are disclosed in terms of a serial-feed-back A/D converter that performs an A/D conversion through a plurality of cycles equal in number to the number of bits in the digital output word. In each cycle a comparison voltage is tested to determine if the bit output for the cycle is high or low. The comparison voltage is the amplified difference of the comparison voltage for the preceding cycle and another reference signal. The scale factor for the amplification of the difference between the two signals is one value if the bit value for the preceding cycle was high, and another complementary value if the bit value for the preceding cycle is low.

Abstract: Signal information is converted between analog and digital form in a two-step process employing conversion apparatus having stable, but not necessarily highly accurate components. The component tolerances on such conversion apparatus are much greater than those normally allowed on conventional conversion apparatus of equal accuracy. In an A/D conversion, an analog signal is first converted into an (n+m)-bit digital word in a special purpose digital code unique to the specific A/D conversion apparatus. The (n+m)-bit word is then translated into an n-bit word in binary digital code in accordance with a predetermined relationship therebetween. In a D/A conversion, an n-bit digital word in a binary digital code is first translated into a corresponding (n+m)-bit digital word in the special purpose digital code. The (n+m)-bit word is then converted into an equivalent analog signal; the latter step being performed by a conversion apparatus unique to the special purpose digital code.

Abstract: Signal information is converted between analog and digital form in a two-step process employing conversion apparatus having stable, but not necessarily highly accurate components. The component tolerances on such conversion apparatus are much greater than those normally allowed on conventional conversion apparatus of equal accuracy. In an A/D conversion, an analog signal is first converted into an (n+m)-bit digital word in a special purpose digital code unique to the specific A/D conversion apparatus. The (n+m)-bit word is then translated into an n-bit word in binary digital code in accordance with a predetermined relationship therebetween. In a D/A conversion, an n-bit digital word in a binary digital code is first translated into a corresponding (n+m)-bit digital word in the special purpose digital code. The (n+m)-bit word is then converted into an equivalent analog signal; the latter step being performed by a conversion apparatus unique to the special purpose digital code.

Abstract: A Fault-Tolerant Multi-Computer System for control applications is disclosed. The system has a plurality of Computers (10a-10n), each having an assigned set of tasks which it is capable of executing. No one Computer in the system acts as a master and no one Computer executes all of the tasks. Communication between the Computers is by individual communication links (16, 18, 20) over which each Computer sends information directly to all other Computers in the system. Each Computer comprises an Applications Computer (100) and an Operations Controller (200). The Operations Controller receives messages over the communication links and selects, from the assigned tasks, the tasks to be performed by the associated Applications Computer. Each Operations Controller includes a fault handler which checks the messages received from the other Computers. The fault handlers send and receive error messages, over the communication links, to assist in the identification of a faulty Computer.

Abstract: A communication system for a multiple computer or distributed computing system is disclosed. The communication system comprises a set of individual communication links. Each computer (10a through 10n) has its own communication link (16, 18, and 20), over which it alone can transmit messages to every other computer in the system. Each computer (10a through 10n) includes a plurality of receivers, one receiver for each computer in the system. Each receiver is connected to one of the communication links, and only receives messages transmitted by the single computer which transmits messages over that communication link.

Abstract: A method and apparatus for converting between analog signals and corresponding digital signals that is accurate relative to the actual value of the input signal, and not relative to the upper limit on the analog input signal. The method and apparatus are disclosed in terms of a serial-feed-back A/D converter that performs an A/D conversion through a plurality of cycles equal in number to the number of bits in the digital output word. In each cycle a comparison voltage is tested to determine if the bit output for the cycle is high or low. The comparison voltage is the amplified difference of the comparison voltage for the preceding cycle and another reference signal. The scale factor for the amplification of the difference between the two signals is one value if the bit value for the preceding cycle was high, and another complementary value if the bit value for the preceding cycle is low.

Abstract: A task communicator for each computer in a multiple computer system is disclosed. The task communicator provides communication of data values between cooperating tasks executed by different computers. The task communicator comprises a data values table (804) storing the current data values required for the execution of each task assigned to its computer. A store data value module (802) which stores the data values received from the other computers in the data values table. A task dispatcher (806) which copies the data values required for the execution of a selected task into a task input table (810). A release task module (814), which releases for execution the identified task and data values stored in the task input table. A task output table (812) storing the values of the data resulting from the execution of each task by its own computer.

Abstract: The invention is a synchronizer for synchronizing the operation of the computers in a multiple computer system. One synchronizer is associated with each computer, and it regularly generates signals to initiate the operations in its own computer which must be synchronized among the computers. The synchronizer comprises a start synchronizer module (458), a sampling data table including a sampling timer (460), a check sampling timer module (464), and a find sampling number agreement module (466). The sampling period timer times a sampling period having a predetermined time interval. At the end of each sampling period, the check sampling timer module sends a sampling number message containing a new sampling number. The find sampling number agreement module (466) generates a voted sampling number when sampling number messages received from like synchronizers in a predetermined number of computers contain the same sampling number.

Abstract: An operations controller for each computer in a multiple computer system is disclosed. Each operations controller controls the operations of its associated computer, so that all of the computers cooperate to perform system functions in a fault-tolerant manner. Each operations controller comprises a fault handler (204), a scheduler (206), a task communicator (208), plus a transmitter (212) and requisite receivers (202) which receive and send messages to all the other computers in the system. The fault handler (204) checks each message received and decides which computers are operating correctly and which are faulty. A scheduler (206) selects each task its own computer will execute, from the tasks assigned to its own computer. A task communicator (208) assembles the data values required for the execution of the selected task, and forwards this data to the computer for execution.

Abstract: A fault handler for each computer in a multiple computer system is disclosed, which excludes faulty computers from participating in the operation of the multiple computer system. The fault handler comprises one or more message checkers (216, 218, 220, 222 and 224) and a fault tolerator (228). In the disclosed embodiment, the fault handler further includes a synchronizer (226) for synchronizing the operation of the associated computer with the operation of the other computers in the system. The checker modules check each message received from the other computers, and forward the messages to the fault tolerator. From error messages received from the other computers and errors detected by its own checker modules, the fault tolerator (228) decides which computers are faulty and discards the messages received from those computers. Only messages received from non-faulty computers are passed on for further processing.

Abstract: Signal information is converted between analog and digital form in a two-step process employing conversion apparatus having stable, but not necessarily highly accurate components. The component tolerances on such conversion apparatus are much greater than those on such conversion apparatus are much greater than those normally allowed on conventional conversion apparatus of equal accuracy. In an A/D conversion, an analog signal is first converted into an (n+m)-bit digital word in a special purpose digital code unique to the specific A/D conversion apparatus. The (n+m)-bit word is then translated into an n-bit word in binary digital code in accordance with a predetermined relationship therebetween. In a D/A conversion, an n-bit digital word in a binary digital code is first translated into a corresponding (n+m)-bit digital word in the special purpose digital code.

Abstract: A scheduler for selecting and scheduling the tasks to be executed by a computer in a multiple computer system is disclosed. One scheduler is associated with each computer, and the schedulers coordinate their operation by sending and receiving messages. Each scheduler comprises a status table (604) storing the status of each task assigned to its computer, and a scheduling status table (608) storing the tasks recently selected for execution by the computer. The scheduler further includes a record data ready module (600) which records in the status table (604) the reception of the data variables required for the execution of each task. A completed task recorder (612) records which tasks have been executed by itself or any other computer in the system. An unselected/selected task recorder records the selection and unselection of tasks by other computers. A task unselector records the tasks which have been unselected by itself.