Patents by Inventor Arlo J. Aude

Arlo J. Aude has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8929500
    Abstract: The disclosed clock-data recovery architecture includes out-of-lock (including false lock) detection. Out-of-lock detection is accomplished by sampling retimed/recovered data with positive and negative edges of the received data. In example embodiments, an out-of-lock condition is determined either by detecting the occurrence of, or counting, missed edges corresponding to the failure of received data sampling to detect corresponding positive/negative edges of the retimed/recovered data.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: January 6, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Tonmoy S. Mukherjee, Arlo J. Aude
  • Patent number: 8633756
    Abstract: Low voltage differential signaling (LVDS) circuitry and method for dynamically controlling the common mode voltage at the input of an LVDS receiver. The common mode voltage of the incoming LVDS signal is monitored. The common mode voltage at the input of the LVDS receiver is clamped at a clamp voltage when the common mode voltage of the incoming LVDS signal is less than a predetermined voltage, and allowed to track it otherwise.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: January 21, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Arlo J. Aude, Soumya Chandramouli
  • Patent number: 8476934
    Abstract: Differential signal detection circuitry with an integrated reference voltage. The reference voltage is added as an offset to the output voltage, and its integration ensures that variations in the reference voltage closely track variations in the signal. Accordingly, the detection threshold for the signal being detected remains more consistent over variations in the circuit manufacturing process, power supply voltage and operating temperature.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: July 2, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Arlo J. Aude, Soumya Chandramouli
  • Patent number: 8416112
    Abstract: Circuitry and method for digital-to-analog current signal conversion with phase interpolation. For an n-bit digital-to-analog converter (DAC), the number 2n control bits normally required can be reduced to 2(n-1) by jointly controlling pairs of the current sources with one of the 2(n-1) current control bits and inverses of two other ones of the 2(n-1) current control bits.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: April 9, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Arlo J. Aude, Steven E. Finn
  • Publication number: 20130021186
    Abstract: Circuitry and method for digital-to-analog current signal conversion with phase interpolation. For an n-bit digital-to-analog converter (DAC), the number 2n control bits normally required can be reduced to 2(n-1) by jointly controlling pairs of the current sources with one of the 2(n-1) current control bits and inverses of two other ones of the 2(n-1) current control bits.
    Type: Application
    Filed: July 21, 2011
    Publication date: January 24, 2013
    Applicant: National Semiconductor Corporation
    Inventors: Arlo J. Aude, Steven E. Finn
  • Publication number: 20130021082
    Abstract: Low voltage differential signaling (LVDS) circuitry and method for dynamically controlling the common mode voltage at the input of an LVDS receiver. The common mode voltage of the incoming LVDS signal is monitored. The common mode voltage at the input of the LVDS receiver is clamped at a clamp voltage when the common mode voltage of the incoming LVDS signal is less than a predetermined voltage, and allowed to track it otherwise.
    Type: Application
    Filed: July 21, 2011
    Publication date: January 24, 2013
    Applicant: National Semiconductor Corporation
    Inventors: Arlo J. Aude, Soumye Chandramouli
  • Publication number: 20130021081
    Abstract: Differential signal detection circuitry with an integrated reference voltage. The reference voltage is added as an offset to the output voltage, and its integration ensures that variations in the reference voltage closely track variations in the signal. Accordingly, the detection threshold for the signal being detected remains more consistent over variations in the circuit manufacturing process, power supply voltage and operating temperature.
    Type: Application
    Filed: July 21, 2011
    Publication date: January 24, 2013
    Applicant: National Semiconductor Corporation
    Inventors: Arlo J. Aude, Soumya Chandramouli
  • Patent number: 6859387
    Abstract: Three-state binary adders are disclosed for use in pipelined analog-to-digital converters. According to one advantageous embodiment, a three-state binary adder is provided for use in a digital signal processing system. The three-state binary adder is operable to generate binary codes consisting of three states, namely, “00”, “01” and “10.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: February 22, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Arlo J. Aude, Laurence D. Lewicki
  • Patent number: 6710732
    Abstract: Three-state binary adders with endpoint correction are employed in a digital signal processing system within a pipelined analog-to-digital converter. The adder is operable to add received signals. The endpoint correction circuitry, which is associated with the adder, is operable to (i) use ±½ full scale tip voltages and to (ii) generate over and under indicators.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: March 23, 2004
    Assignee: National Semiconductor Corporation
    Inventor: Arlo J. Aude
  • Patent number: 6559787
    Abstract: There is disclosed a comparator comprising: 1) a first comparison circuit capable of receiving an input signal, wherein the first comparison circuit is enabled and compares the signal when a received LATCH signal is enabled and is disabled when the received LATCH signal is disabled; and 2) a second comparison circuit coupled to the input signal in parallel with the first comparison circuit, wherein an input stage of the second comparison circuit is substantially identical to an input stage of the first comparison circuit. The second comparison circuit is enabled and compares the input signal when the received LATCH is signal is disabled and is disabled when the received LATCH signal is enabled.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: May 6, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Arlo J. Aude, Laurence D. Lewicki, Jitendra Mohan
  • Patent number: 6486821
    Abstract: There is disclosed an amplifier for operating from a power supply having a first voltage level. The amplifier comprises: 1) a plurality of thick-oxide field effect transistors, each of the plurality of thick-oxide field effect transistors having a relatively thick oxide layer and fabricated using a first process such that the each thick-oxide field effect transistor can withstand a gate-to-source difference, a gate-to-drain difference, and a gate-to-bulk difference at least equal to a first maximum operating voltage, wherein the first.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: November 26, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Arlo J. Aude, Laurence D. Lewicki, Jitendra Mohan
  • Patent number: 6469652
    Abstract: There is disclosed, for use in an analog to digital (ADC) converter, an ADC stage that receives a differential analog input signal, quantizes the differential analog input signal to a plurality of digital bits, and generates an output residue signal corresponding to a quantization error of the differential analog input signal.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: October 22, 2002
    Assignee: National Semiconductor Corporation
    Inventor: Arlo J. Aude
  • Patent number: 6445250
    Abstract: There is disclosed an amplifier comprising: 1) a plurality of cascaded NMOS differential amplifier stages, wherein a first one of the plurality of cascaded NMOS differential amplifier stages is coupled to at least one input signal; 2) a PMOS differential amplifier stage having a first input coupled to a first NMOS differential output of a last one of the plurality of cascaded NMOS differential amplifier stages and a second input coupled to a second NMOS differential output of the last cascaded NMOS differential amplifier stage, wherein the PMOS differential amplifier comprises a first diode-connected PMOS load transistor having a gate and a drain connected to ground and a second diode-connected PMOS load transistor having a gate and a drain connected to ground; and 3) an output differential amplifier stage comprising: a) load transistors comprising a third PMOS transistor having a gate and a drain connected together and a source connected to a power supply rail and a fourth PMOS transistor having a gate coupl
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: September 3, 2002
    Assignee: National Semiconductor Corporation
    Inventor: Arlo J. Aude
  • Publication number: 20020097092
    Abstract: There is disclosed an amplifier comprising: 1) a plurality of cascaded NMOS differential amplifier stages, wherein a first one of the plurality of cascaded NMOS differential amplifier stages is coupled to at least one input signal; 2) a PMOS differential amplifier stage having a first input coupled to a first NMOS differential output of a last one of the plurality of cascaded NMOS differential amplifier stages and a second input coupled to a second NMOS differential output of the last cascaded NMOS differential amplifier stage, wherein the PMOS differential amplifier comprises a first diode-connected PMOS load transistor having a gate and a drain connected to ground and a second diode-connected PMOS load transistor having a gate and a drain connected to ground; and 3) an output differential amplifier stage comprising: a) load transistors comprising a third PMOS transistor having a gate and a drain connected together and a source connected to a power supply rail and a fourth PMOS transistor having a gate coupl
    Type: Application
    Filed: May 12, 2000
    Publication date: July 25, 2002
    Inventor: Arlo J. Aude