Abstract: Automated test procedures, carried out under software control, can be employed to test a device, testing individual pins, and/or groups of pins, to detect and diagnose or characterize various types of failures. A distributed FA system includes a shared database for device definitions, test setups, and test results. Test platforms provide I/O curve tracing which can provide both a qualitative visual representation and a quantitative measured performance. The disclosed system enables and exploits front line testing of devices in the field. Response to the customer can be nearly immediate. Eliminate “false returns” by differentiation of use versus a real quality issue.

Abstract: Various embodiments related to identifying a candidate defect region in a semiconductor device are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; generating a physical representation of portion of a logical design of the semiconductor device, the physical representation including location information for physical instantiations of logical cells and logical interconnections included in the portion of the logical design; identifying a suspect logical region in the physical representation, the suspect logical region including a portion of the logical cells and the logical interconnections electrically connected with the scan chain; generating a candidate defect region within the semiconductor device, the candidate defect region being defined, via the physical representation, to include the physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.

Abstract: Automated test procedures, carried out under software control, can be employed to test a device, testing individual pins, and/or groups of pins, to detect and diagnose or characterize various types of failures. A distributed FA system includes a shared database for device definitions, test setups, and test results. Test platforms provide I/O curve tracing which can provide both a qualitative visual representation and a quantitative measured performance. The disclosed system enables and exploits front line testing of devices in the field. Response to the customer can be nearly immediate. Eliminate “false returns” by differentiation of use versus a real quality issue.

Abstract: Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination.

Abstract: Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination.

Abstract: Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination.

Abstract: Various embodiments related to identifying regions including physical defects in semiconductor devices are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; identifying a suspect logical region including a plurality of logic cones electrically connected with the scan chain; adjusting a scope of the suspect logical region by simulating data flow within the logic cones, generating simulated scan chain output based on the simulated data flow within the logic cones, and excluding at least one of the logic cones from the suspect logical region based on a comparison of the electrical test mismatch and the simulated scan chain output; after adjusting the scope of the suspect logical region, generating a candidate defect region, the candidate defect region being defined to include physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.

Abstract: Various embodiments related to identifying a candidate defect region in a semiconductor device are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; generating a physical representation of portion of a logical design of the semiconductor device, the physical representation including location information for physical instantiations of logical cells and logical interconnections included in the portion of the logical design; identifying a suspect logical region in the physical representation, the suspect logical region including a portion of the logical cells and the logical interconnections electrically connected with the scan chain; generating a candidate defect region within the semiconductor device, the candidate defect region being defined, via the physical representation, to include the physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.

Abstract: Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination.

Abstract: Various embodiments related to identifying regions including physical defects in semiconductor devices are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; identifying a suspect logical region including a plurality of logic cones electrically connected with the scan chain; adjusting a scope of the suspect logical region by simulating data flow within the logic cones, generating simulated scan chain output based on the simulated data flow within the logic cones, and excluding at least one of the logic cones from the suspect logical region based on a comparison of the electrical test mismatch and the simulated scan chain output; after adjusting the scope of the suspect logical region, generating a candidate defect region, the candidate defect region being defined to include physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.

Abstract: An ATE system uses a single digital to analog converter and a single analog line for defining the reference voltage levels of a plurality of pin drivers and pin sensors. An advantage of using a single DAC is that the number of components for routing the reference voltage signals is reduced. Digital values for each high and low reference voltage level for each pin driver and each pin sensor are stored in memory. Such memory is addressed sequentially reference value by reference value, converted to analog format and routed along one common analog wire to a plurality of sample and hold circuits. The plurality of sample and hold circuits receive a pin driver/sensor address and the common analog signal. The address enables one of the plurality of sample and hold circuits and selects only one output line of the enabled sample and hold circuit. Such output line is coupled to a given reference terminal (e.g., reference high or reference low) of a given pin driver or a given pin sensor.

Abstract: A modular ATE system includes a plurality of test modules and a receiver for use with a variety of fixtures to which printed circuit boards are to be coupled. Each test module includes a plurality of pin cards controlled by a single module controller. Multiple test module are included for testing a variety of functions. Test signals are generated by discrete sets of pin cards and controllers, then output to the receiver for interconnection to a fixture and printed circuit board(s) under test. A substantially wireless receiver is provided, including a translation board for electrically coupling test module pin cards to the fixture. By eliminating wiring and cabling by using a prefabricated translation board, noise is substantially reduced and test signal quality improved. The translation board defines prescribed signal mapping for interconnecting the I/O pins of ATE pin cards to the underside of the fixture. Different translation boards may have different mappings.

Abstract: A tri-state pin driver is formed in part, along with a pin sensor, on an integrated circuit. A pin driver and sensor are coupled to a common pin of a device under test. In normal mode, the pin driver drives a test signal. In high impedance mode, the pin driver is at a high impedance, enabling a sensor to monitor a response signal. The pin driver includes a driver stage formed off-chip by a pair of power transistors operated in the active region. The large power transistors enable a large current (i.e., +/-500 mA) to be sourced or sunk so as to drive a device under test and back-drive preceding circuits. Operating in the active region enables faster logic state transition times, and thus, a fast test rate, while reducing undesirable signal distortion. A predriver stage is configured as a unity-gain emitter follower. The predriver stage includes first and second signal paths. Each signal path includes a pair of transistors configured, during normal mode, as a transmission gate.