Abstract: Disclosed are devices, apparatuses, systems, computer readable media, and methods for improving the security of circuitry designs using HDL code. In one aspect a method is disclosed. the method includes receiving a hardware design language (HDL) representation of a circuit; inserting flow tracking into the HDL representation, wherein the flow tracking adds one or more security labels that are tracked throughout the circuit; and generating an enhanced HDL representation of the circuit, wherein the enhanced HDL representation comprises the HDL representation and the flow tracking, wherein the enhanced representation including the one or more security labels that are tracked throughout the circuit enables a security determination a model for tracking timing-based information flows through HDL code is disclosed. The disclosed technology is used to verify security properties on a variety of equipment including crypto cores, bus architectures, caches and arithmetic modules.

Abstract: Disclosed are devices, apparatuses, systems, computer readable media, and methods for improving the security of circuitry designs using HDL code. In one aspect a method is disclosed. the method includes receiving a hardware design language (HDL) representation of a circuit; inserting flow tracking into the HDL representation, wherein the flow tracking adds one or more security labels that are tracked throughout the circuit; and generating an enhanced HDL representation of the circuit, wherein the enhanced HDL representation comprises the HDL representation and the flow tracking, wherein the enhanced representation including the one or more security labels that are tracked throughout the circuit enables a security determination a model for tracking timing-based information flows through HDL code is disclosed. The disclosed technology is used to verify security properties on a variety of equipment including crypto cores, bus architectures, caches and arithmetic modules.