Abstract: Systems and methods for gate driver with field-adjustable undervoltage lockout (UVLO) are disclosed. A gate driver system comprises a control circuit and a driver circuit. The driver circuit incorporates a field-adjustable UVLO, a control logic, and an inverter. The level of the field-adjustable UVLO is adjustable by an external circuit, which can be a resistor based voltage divider. By setting the UVLO level externally adjustable and by moving a reference ground to the external voltage divider, the gate driver system is able to implement gate control for various load without needing extra ground pin.

Abstract: A method for using driver circuitry to drive a load having an unknown impedance magnitude includes (a) in a configuration mode of the driver circuitry, determining a required power supply voltage for a driver stage to drive the load, and (b) in a driving mode of the driver circuitry, (1) driving the load via the driver stage in response to an input signal, and (2) controlling a power supply to provide the required power supply voltage to the driver stage as a static voltage, while driving the load via the driver stage in response to the input signal.

Abstract: A method for quickly shutting down a transistor in a switching circuit includes (a) generating a feedback signal associated with current flowing through the transistor, (b) transmitting the feedback signal through an isolating device to a controller, (c) detecting an over-current condition in the switching circuit without transmitting information through the isolating device, and (d) shutting-down the transistor in response to detecting the over-current condition, without transmitting information through the isolating device.

Abstract: Systems and methods for gate driver with field-adjustable undervoltage lockout (UVLO) are disclosed. A gate driver system comprises a control circuit and a driver circuit. The driver circuit incorporates a field-adjustable UVLO, a control logic, and an inverter. The level of the field-adjustable UVLO is adjustable by an external circuit, which can be a resistor based voltage divider. By setting the UVLO level externally adjustable and by moving a reference ground to the external voltage divider, the gate driver system is able to implement gate control for various load without needing extra ground pin.

Abstract: Systems and methods for gate driver with field-adjustable undervoltage lockout (UVLO) are disclosed. A gate driver system comprises a control circuit and a driver circuit. The driver circuit incorporates a field-adjustable UVLO, a control logic, and an inverter. The level of the field-adjustable UVLO is adjustable by an external circuit, which can be a resistor based voltage divider. By setting the UVLO level externally adjustable and by moving a reference ground to the external voltage divider, the gate driver system is able to implement gate control for various load without needing extra ground pin.

Abstract: A method for using driver circuitry to drive a load having an unknown impedance magnitude includes (a) in a configuration mode of the driver circuitry, determining a required power supply voltage for a driver stage to drive the load, and (b) in a driving mode of the driver circuitry, (1) driving the load via the driver stage in response to an input signal, and (2) controlling a power supply to provide the required power supply voltage to the driver stage as a static voltage, while driving the load via the driver stage in response to the input signal.

Abstract: Systems and methods for gate driver with field-adjustable undervoltage lockout (UVLO) are disclosed. A gate driver system comprises a control circuit and a driver circuit. The driver circuit incorporates a field-adjustable UVLO, a control logic, and an inverter. The level of the field-adjustable UVLO is adjustable by an external circuit, which can be a resistor based voltage divider. By setting the UVLO level externally adjustable and by moving a reference ground to the external voltage divider, the gate driver system is able to implement gate control for various load without needing extra ground pin.

Abstract: A circuit for monitoring the health of the transformers is disclosed. In an implementation, the circuit includes a transformer that provides an input signal and a pulse generator that generates a pulse signal. An analog-to-digital converter receives a combined signal that includes the input signal and the pulse signal, and the analog-to-digital converter converts the combined signal to a digital representation of the combined signal. The circuit includes a first digital filter and a second digital filter that are connected to the analog-to-digital converter. The first digital filter reconstructs an amplitude characteristic of the input signal, and the second digital filter reconstructs the pulse signal. The circuit also includes a controller that indicates a short circuit or an open circuit associated with the transformer based upon a value of the reconstructed pulse signal.

Abstract: Techniques are described for providing highly integrated and configurable IO ports for integrated circuits that can be individually configured for a variety of general purpose digital or analog functions, such as multiple channel analog-to-digital converters (ADC), multiple channel digital-to-analog converters (DAC), multiplexers, GPIOs, analog switches, switch and multiplexers, digital logic level translators, comparators, temperature sensors and relays, and so forth. The configurations of individual ports can be set by a configuration register that can, for instance, designate the function and voltage range of the port without impacting the other ports. In embodiments, logic mapping of a port order sequence can be defined. A data register can also be included for handling microcontroller commands and storing conversion results from, for instance, a port functioning as an ADC input port.

Abstract: A system includes a divider on a first side of electrically isolated circuitry for receiving a clock signal having a characteristic frequency and dividing the clock signal by a characteristic value. The system also includes an optical link coupled with the divider for receiving the divided clock signal and transmitting the divided clock signal from the first side of the electrically isolated circuitry to a second side of the electrically isolated circuitry. The system further includes a phase-locked loop on the second side of the electrically isolated circuitry. The phase-locked loop is coupled with the optical link and configured to receive the divided clock signal from the optical link and generate a second signal at a multiple of a characteristic frequency of the divided clock signal so that the second signal comprises the characteristic frequency of the clock signal received by the divider circuitry.

Abstract: A system includes a light emitting device on a first side of electrically isolated circuitry for transmitting an optical signal to a second side of the electrically isolated circuitry. The system also includes an optical receiver on the second side of the electrically isolated circuitry for receiving the optical signal from the light emitting device. The system further includes a sensor coupled with the optical receiver for sampling the intensity of the optical signal received by the optical receiver.

Abstract: A system includes a light emitting device on a first side of electrically isolated circuitry for transmitting an optical signal to a second side of the electrically isolated circuitry. The system also includes a driver for driving the light emitting device at an operational characteristic. The system further includes an optical receiver on the second side of the electrically isolated circuitry for receiving the optical signal from the light emitting device. The system also includes a sensor coupled with the optical receiver for sampling the intensity of the optical signal received by the optical receiver. The sensor is communicatively coupled with the driver and configured to transmit the sampled intensity of the optical signal received from the light emitting device to the driver, and the driver is configured to adjust the operational characteristic of the light emitting device based upon the sampled intensity of the optical signal.

Abstract: Techniques are described for providing highly integrated and configurable IO ports for integrated circuits that can be individually configured for a variety of general purpose digital or analog functions, such as multiple channel analog-to-digital converters (ADC), multiple channel digital-to-analog converters (DAC), multiplexers, GPIOs, analog switches, switch and multiplexers, digital logic level translators, comparators, temperature sensors and relays, and so forth. The configurations of individual ports can be set by a configuration register that can, for instance, designate the function and voltage range of the port without impacting the other ports. In embodiments, logic mapping of a port order sequence can be defined. A data register can also be included for handling microcontroller commands and storing conversion results from, for instance, a port functioning as an ADC input port.

Abstract: Techniques are described for providing highly integrated and configurable IO ports for integrated circuits that can be individually configured for a variety of general purpose digital or analog functions, such as multiple channel analog-to-digital converters (ADC), multiple channel digital-to-analog converters (DAC), multiplexers, GPIOs, analog switches, switch and multiplexers, digital logic level translators, comparators, temperature sensors and relays, and so forth. The configurations of individual ports can be set by a configuration register that can, for instance, designate the function and voltage range of the port without impacting the other ports. In embodiments, logic mapping of a port order sequence can be defined. A data register can also be included for handling microcontroller commands and storing conversion results from, for instance, a port functioning as an ADC input port.

Abstract: An integrated circuit device, set forth by way of example and not limitation, includes an IC package provided with a plurality of leads and enclosing: a) a buffer amplifier, b) a switching-mode power amplifier having an input coupled to the output of the buffer amplifier and having an output coupled to at least one of the plurality of leads, and c) a digital controller. A method, set forth by way of example and not limitation, for controlling the power output of a RF transmitter circuit without the need for an attenuator includes developing a signal source, applying the signal source to a buffer amplifier to provide an amplified signal, applying the amplified signal to a switching-mode power amplifier to provide a power output signal, and controlling a gain of the switching-mode power amplifier in response to a digital command.

Abstract: Techniques are described for providing highly integrated and configurable IO ports for integrated circuits that can be individually configured for a variety of general purpose digital or analog functions, such as multiple channel analog-to-digital converters (ADC), multiple channel digital-to-analog converters (DAC), multiplexers, GPIOs, analog switches, switch and multiplexers, digital logic level translators, comparators, temperature sensors and relays, and so forth. The configurations of individual ports can be set by a configuration register that can, for instance, designate the function and voltage range of the port without impacting the other ports. In embodiments, logic mapping of a port order sequence can be defined. A data register can also be included for handling microcontroller commands and storing conversion results from, for instance, a port functioning as an ADC input port.

Abstract: An integrated circuit device, set forth by way of example and not limitation, includes an IC package provided with a plurality of leads and enclosing: a) a buffer amplifier, b) a switching-mode power amplifier having an input coupled to the output of the buffer amplifier and having an output coupled to at least one of the plurality of leads, and c) a digital controller. A method, set forth by way of example and not limitation, for controlling the power output of a RF transmitter circuit without the need for an attenuator includes developing a signal source, applying the signal source to a buffer amplifier to provide an amplified signal, applying the amplified signal to a switching-mode power amplifier to provide a power output signal, and controlling a gain of the switching-mode power amplifier in response to a digital command.

Abstract: An integrated circuit device, set forth by way of example and not limitation, includes an IC package provided with a plurality of leads and enclosing: a) a buffer amplifier, b) a switching-mode power amplifier having an input coupled to the output of the buffer amplifier and having an output coupled to at least one of the plurality of leads, and c) a digital controller. A method, set forth by way of example and not limitation, for controlling the power output of a RF transmitter circuit without the need for an attenuator includes developing a signal source, applying the signal source to a buffer amplifier to provide an amplified signal, applying the amplified signal to a switching-mode power amplifier to provide a power output signal, and controlling a gain of the switching-mode power amplifier in response to a digital command.

Abstract: In an embodiment, set forth by way of example and not limitation, a receiver with automatic gain includes a receiver stage, an AGC stage, and a digital processor which collectively define an AGC loop. Preferably, the AGC stage has a control circuit and a feedback circuit with matched transfer characteristics. A digital processor is operative to develop a gain control signal to set a desired gain level of the receiver stage to an optimal level based upon a waveform analysis derived from the gain feedback signal.

Abstract: In an embodiment, set forth by way of example and not limitation, a receiver with automatic gain includes a receiver stage, an AGC stage, and a digital processor which collectively define an AGC loop. Preferably, the AGC stage has a control circuit and a feedback circuit with matched transfer characteristics. A digital processor is operative to develop a gain control signal to set a desired gain level of the receiver stage to an optimal level based upon a waveform analysis derived from the gain feedback signal.