Abstract: A Dynamic Digital Pre-Distortion (DDPD) system is disclosed to rapidly correct power amplifier (PA) non-linearity and memory effects. To perform pre-distortion, a DDPD engine predistorts an input signal in order to cancel PA nonlinearities as the signal is amplified by the PA. The DDPD engine is implemented as a composite of one linear filter and N?1 high order term linear filters. The bank of linear filters have programmable complex coefficients. To compute the coefficients, samples from the transmit path and a feedback path are captured, and covariance matrices A and B are computed using optimized hardware. After the covariance matrices are computed, Gaussian elimination processing may be employed to compute the coefficients. Mathematical and hardware optimizations may be employed to simplify and reduce the number of multiplication operands and other operations, which can enable the DDPD system to fit within a single chip.

Abstract: A Dynamic Digital Pre-Distortion (DDPD) system is disclosed to rapidly correct power amplifier (PA) non-linearity and memory effects. To perform pre-distortion, a DDPD engine predistorts an input signal in order to cancel PA nonlinearities as the signal is amplified by the PA. The DDPD engine is implemented as a composite of one linear filter and N?1 high order term linear filters. The bank of linear filters have programmable complex coefficients. To compute the coefficients, samples from the transmit path and a feedback path are captured, and covariance matrices A and B are computed using optimized hardware. After the covariance matrices are computed, Gaussian elimination processing may be employed to compute the coefficients. Mathematical and hardware optimizations may be employed to simplify and reduce the number of multiplication operands and other operations, which can enable the DDPD system to fit within a single chip.

Abstract: A Dynamic Digital Pre-Distortion (DDPD) system is disclosed to rapidly correct power amplifier (PA) non-linearity and memory effects. To perform pre-distortion, a DDPD engine predistorts an input signal in order to cancel PA nonlinearities as the signal is amplified by the PA. The DDPD engine is implemented as a composite of one linear filter and N?1 high order term linear filters. The bank of linear filters have programmable complex coefficients. To compute the coefficients, samples from the transmit path and a feedback path are captured, and covariance matrices A and B are computed using optimized hardware. After the covariance matrices are computed, Gaussian elimination processing may be employed to compute the coefficients. Mathematical and hardware optimizations may be employed to simplify and reduce the number of multiplication operands and other operations, which can enable the DDPD system to fit within a single chip.

Abstract: A performance monitor for generating a digital error signal based upon an RF input signal and an amplified RF output signal is provided.

Abstract: A Dynamic Digital Pre-Distortion (DDPD) system is disclosed to rapidly correct power amplifier (PA) non-linearity and memory effects. To perform pre-distortion, a DDPD engine predistorts an input signal in order to cancel PA nonlinearities as the signal is amplified by the PA. The DDPD engine is implemented as a composite of one linear filter and N?1 high order term linear filters. The bank of linear filters have programmable complex coefficients. To compute the coefficients, samples from the transmit path and a feedback path are captured, and covariance matrices A and B are computed using optimized hardware. After the covariance matrices are computed, Gaussian elimination processing may be employed to compute the coefficients. Mathematical and hardware optimizations may be employed to simplify and reduce the number of multiplication operands and other operations, which can enable the DDPD system to fit within a single chip.

Abstract: A pre-distorter is provided for distorting an RF input signal to provide a pre-distorted radio frequency (RF) input signal to an amplifier that provides an amplified RF output signal, wherein the RF input signal has an envelope. The pre-distorter includes: a radio-frequency signal processing circuit that distorts the RF input signal according to a polynomial of powers of the envelope, each power of the envelope being weighted by a corresponding pre-distortion weight; and a performance monitor operable to compare a version of the amplified RF output signal to a delayed version of the RF input signal to provide an error signal, wherein the performance monitor is configured to iteratively adapt the coefficients based upon a gradient of a cost function, the cost function being a function of the error signal.

Abstract: A Dynamic Digital Pre-Distortion (DDPD) system is disclosed to rapidly correct power amplifier (PA) non-linearity and memory effects. To perform pre-distortion, a DDPD engine predistorts an input signal in order to cancel PA nonlinearities as the signal is amplified by the PA. The DDPD engine is implemented as a composite of one linear filter and N?1 high order term linear filters. The bank of linear filters have programmable complex coefficients. To compute the coefficients, samples from the transmit path and a feedback path are captured, and covariance matrices A and B are computed using optimized hardware. After the covariance matrices are computed, Gaussian elimination processing may be employed to compute the coefficients. Mathematical and hardware optimizations may be employed to simplify and reduce the number of multiplication operands and other operations, which can enable the DDPD system to fit within a single chip.

Abstract: A Dynamic Digital Pre-Distortion (DDPD) system is disclosed to rapidly correct power amplifier (PA) non-linearity and memory effects. To perform pre-distortion, a DDPD engine predistorts an input signal in order to cancel PA nonlinearities as the signal is amplified by the PA. The DDPD engine is implemented as a composite of one linear filter and N?1 high order term linear filters. The bank of linear filters have programmable complex coefficients. To compute the coefficients, samples from the transmit path and a feedback path are captured, and covariance matrices A and B are computed using optimized hardware. After the covariance matrices are computed, Gaussian elimination processing may be employed to compute the coefficients. Mathematical and hardware optimizations may be employed to simplify and reduce the number of multiplication operands and other operations, which can enable the DDPD system to fit within a single chip.

Abstract: A polynomial generator and memory compensator module is provided that includes: a first bank of delay filters for generating current and delayed versions of the envelope for an RF input signal and for the square of the envelope, a polynomial generator for generating polynomials using the current and delayed versions of the envelope, each polynomial being weighted according to pre-distortion weights; an adder for adding the polynomials to provide a pre-distortion signal for pre-distorting the RF input signal to provide a pre-distorted RF input signal such that a power amplifier amplifying the pre-distorted RF input signal provides an amplified RF output signal that reduces a non-linearity of the power amplifier; and a second bank of delay filters for generating delayed versions of the output signal, wherein the adder further adds the delayed versions of the output signal to the polynomials to provide the pre-distortion signal.

Abstract: A Dynamic Digital Pre-Distortion (DDPD) system is disclosed to rapidly correct power amplifier (PA) non-linearity and memory effects. To perform pre-distortion, a DDPD engine predistorts an input signal in order to cancel PA nonlinearities as the signal is amplified by the PA. The DDPD engine is implemented as a composite of one linear filter and N-1 high order term linear filters. The bank of linear filters have programmable complex coefficients. To compute the coefficients, samples from the transmit path and a feedback path are captured, and covariance matrices A and B are computed using optimized hardware. After the covariance matrices are computed, Gaussian elimination processing may be employed to compute the coefficients. Mathematical and hardware optimizations may be employed to simplify and reduce the number of multiplication operands and other operations, which can enable the DDPD system to fit within a single chip.

Abstract: A hybrid multicarrier RF power amplifier linearization architecture combines ACT and feed-forward amplifier stages to achieve high output distortion rejection and enhanced amplifier linearity. A carrier cancellation loop is coupled with a main RF power amplifier stage having parallel RF power amplifiers coupled via intermod-complementing predistortion paths. The carrier cancellation loop is coupled to a feed-forward loop containing a feed-forward RF power amplifier, to produce a composite amplified output signal having very reduced intermodulation products. Vector modulators in the main amplifier and feed-forward amplifier stages are controlled by a digital signal processor, using outputs from various monitoring subsystems, including pilot tone detection, correlator, distortion and power detector circuits.

Abstract: A digitally-based high distortion rejection scheme for linearizing an RF power amplifier employs a digital signal processor, which executes a first signal processing operator in terms of a digital polynomial-based predistortion function that approximates an inverse of the dynamic memory effects in the nonlinear transfer characteristic of the amplifier, and a second signal processing operator that represents an inverse of static non-linearities in the transfer characteristic of the amplifier. The output of this cascaded filter operation is used to control parameters of a vector modulator in the signal input path to the RF power amplifier. The vector modulator thus predistorts the RF input signal, so as to compensate for dynamic memory effects and static non-linearities in the power amplifier.

Abstract: A hybrid multicarrier RF power amplifier linearization architecture combines ACT and feed-forward amplifier stages to achieve high output distortion rejection and enhanced amplifier linearity. A carrier cancellation loop is coupled with a main RF power amplifier stage having parallel RF power amplifiers coupled via intermod-complementing predistortion paths. The carrier cancellation loop is coupled to a feed-forward loop containing a feed-forward RF power amplifier, to produce a composite amplified output signal having very reduced intermodulation products. Vector modulators in the main amplifier and feed-forward amplifier stages are controlled by a digital signal processor, using outputs from various monitoring subsystems, including pilot tone detection, correlator, distortion and power detector circuits.

Abstract: An RF power amplifier linearization architecture contains main and auxiliary path RF amplifiers. A distortion-inverting circuit extracts the distortion component from the output signal of the main amplifier and combines it with a delayed sample of the RF input signal to drive an auxiliary path RF amplifier, via a predistorter. An output quadrature hybrid combines the output of the main and auxiliary path amplifiers. The cascading of the distortion-inverting circuit with the predistorter compensates for the non-linear behavior of the auxiliary path RF power amplifier thereby producing a composite signal at the output quadrature hybrid, in which RF carrier components from each amplifier combine constructively while distortion components cancel.