Abstract: A peripheral unit such as a teletypewriter, associated with a data processor but operating at a relatively slow rate so as to require an interruption of the processor's program when transmitting data, communicates with the processor through an interface unit comprising a sequential network switchable from a quiescent state (D) to an active state (C) via a preparatory state (A) and an intermediate state (B). The sequential network assumes its preparatory state (A) upon the appearance, at the interface unit, of an input/output instruction read out from a program store in the processor and addressed to the associated peripheral unit; the changeover to the intermediate state (B) occurs immediately thereafter if that peripheral unit emits a "data ready" signal (s).