Abstract: A storage subsystem backplane management system includes a storage controller and a service processor. A first backplane including a first management controller is coupled to the storage controller and the service processor. The first backplane is operable to couple a plurality of first drives to the first management controller. A second backplane including a second management controller is coupled to the first management controller. The second backplane is operable to couple a plurality of second drives to the second management controller. The first management controller communicates with the second management controller and creates a virtual management controller that presents to the storage controller and the service processor a virtual backplane including the plurality of first drives and the plurality of second drives when the plurality of first drives are coupled to the first management controller and the plurality of second drives are coupled to the second management controller.

Abstract: A storage subsystem backplane management system includes a storage controller and a service processor. A first backplane including a first management controller is coupled to the storage controller and the service processor. The first backplane is operable to couple a plurality of first drives to the first management controller. A second backplane including a second management controller is coupled to the first management controller. The second backplane is operable to couple a plurality of second drives to the second management controller. The first management controller communicates with the second management controller and creates a virtual management controller that presents to the storage controller and the service processor a virtual backplane including the plurality of first drives and the plurality of second drives when the plurality of first drives are coupled to the first management controller and the plurality of second drives are coupled to the second management controller.

Abstract: An apparatus and method for determining if an interface connector is coupled to a device of a first type, a device of a second type, or to a device of a third type or no device.

Abstract: A system and method for remotely updating a system BIOS. The method includes the steps of providing an updated BIOS to the remote computer system, storing the updated BIOS in a storage device of the remote computer system, setting a BIOS update indicator, rebooting the remote computer system and determining that the BIOS update indicator has been set, replacing the system BIOS with the updated BIOS, and rebooting the remote computer system again. The storage device may be hard drive, with the updated BIOS being stored in an EFI partition of the hard drive.

Abstract: A system and method for remotely updating a system BIOS. The method includes the steps of providing an updated BIOS to the remote computer system, storing the updated BIOS in a storage device of the remote computer system, setting a BIOS update indicator, rebooting the remote computer system and determining that the BIOS update indicator has been set, replacing the system BIOS with the updated BIOS, and rebooting the remote computer system again. The storage device may be hard drive, with the updated BIOS being stored in an EFI partition of the hard drive.

Abstract: A system and method for remotely updating a system BIOS. The method includes the steps of providing an updated BIOS to the remote computer system, storing the updated BIOS in a storage device of the remote computer system, setting a BIOS update indicator, rebooting the remote computer system and determining that the BIOS update indicator has been set, replacing the system BIOS with the updated BIOS, and rebooting the remote computer system again. The storage device may be hard drive, with the updated BIOS being stored in an EFI partition of the hard drive.

Abstract: A method and system for choosing the control processor for booting a multiprocessor system (10) in accordance with a memory (42). A computer system (10) includes a plurality of computer processors (12). The processors (12) use a memory bus (18) to communicate with the main memory (20). A second bus (30) connects the processors (12) to an interupt controller (34). The second bus (30) includes multiple bus request lines (14). An initialization control circuit (32) also communicates with the second bus (30). Memory (42) in the initialization control circuit (32) holds data identifying at least one of the processors (12) and when power is first provided to the system, the initialization control circuit (32) operates to assert signals on the bus request lines (14) such that the identified processor initializes the computer system.