Abstract: Apparatus and methods for programming multiple parameters per pin of an IC are disclosed herein. In certain embodiments, system operation parameters of an IC are set using external component(s) in conjunction with an internal detection circuit of the IC. The internal detection circuit allows for programming of multiple parameters with one pin of the IC, thereby reducing package size, board area, and/or chip complexity. For example, the teachings herein allow for detection of three or more unique parameters or states per pin, significantly reducing the part pin count and board area.

Abstract: This disclosure is generally directed to a multilevel converter with coarse output voltage adjustment circuitry. The multilevel converter may include circuitry to adjust a value of the output voltage by repeating energizing and/or de-energizing phases (e.g., patterns) to generate the output voltage with a desired voltage value. The repeating patterns of energizing and de-energizing phases may be associated with a higher rate of voltage change compared to other multilevel converters. As such, the multilevel converter may adjust the output voltage with a reduced duration based on the higher voltage adjustment rate.

Abstract: Apparatus and methods for programming multiple parameters per pin of an IC are disclosed herein. In certain embodiments, system operation parameters of an IC are set using external component(s) in conjunction with an internal detection circuit of the IC. The internal detection circuit allows for programming of multiple parameters with one pin of the IC, thereby reducing package size, board area, and/or chip complexity. For example, the teachings herein allow for detection of three or more unique parameters or states per pin, significantly reducing the part pin count and board area.

Abstract: A DC-to-DC converter controller configured to generate phase control signals to control a plurality of power stages of a DC-to-DC converter where each power stage includes two phases. The DC-to-DC converter controller is configured to generate the phase control signals in a manner which (a) balances magnitude of current processed among the two phases of each power stage and (b) balances magnitude of current processed among the plurality of power stages.

Abstract: The present invention relates to a voltage converter based on a switching regulator, and more particularly, to systems, devices and methods of dynamically controlling an output of the voltage converter to rapidly transition between different power supply voltages as required in many electronic devices. The switching regulator generates an output supply voltage that tracks a voltage originally provided by an internal DAC. During the supply voltage variation, a step control signal is provided to introduce a supplemental voltage step into the reference voltage before the reference voltage is used to generate the output supply voltage. The switching regulator is thereby overdriven under this supplemental voltage step, enhancing the slew rate and the settling time of the output supply voltage to meet stringent requirements imposed by many electronic devices.

Abstract: Various embodiments of the invention provide extend the switching frequency range of DC/DC multiphase switching regulators in order to overcome prior art frequency limitations in the number of available phases, for example, in low input to output ratio applications. In certain embodiments, this is accomplished by enabling partial overlap between multiple phases using asynchronous logic. The invention is easily scalable without introducing significant silicon area penalties.

Abstract: Various embodiments of the invention provide extend the switching frequency range of DC/DC multiphase switching regulators in order to overcome prior art frequency limitations in the number of available phases, for example, in low input to output ratio applications. In certain embodiments, this is accomplished by enabling partial overlap between multiple phases using asynchronous logic. The invention is easily scalable without introducing significant silicon area penalties.