Abstract: Aspects of the disclosed technology relate to techniques of inserting stress-enhancing filler cells for leakage reduction. Stress analysis is first performed to identify devices with large leakage current in a layout design. An optimization zone in a row of cells that contains one or more of the devices with large leakage current is then determined. Stress-enhancing filler cells are inserted into the optimization zone to replace some or all of the one or more filler cells while placement of the cells in the optimization zone is adjusted based on a leakage reduction analysis.

Abstract: Various aspects of the disclosed technology relate to techniques of determining an across-chip distribution of temperature generated by on-chip devices. Effective thermal conductance and effective thermal capacity for each region of a plurality of regions of a layout design are first extracted. The effective thermal conductance for a region in a metal layer is determined based at least on density information of metal interconnect lines within the region and has components associated with directions of the metal interconnect lines. A thermal circuit is then constructed based on the effective thermal conductance, the effective thermal capacity and heat information of thermal nodes. The heat information of thermal nodes is determined based on an electrical simulation on the integrated circuit associated with the layout design. A thermal simulation is then performed on the thermal circuit to determine temperature information of the thermal nodes.

Abstract: Aspects of the disclosed technology relate to techniques of inserting stress-enhancing filler cells for leakage reduction. Stress analysis is first performed to identify devices with large leakage current in a layout design. An optimization zone in a row of cells that contains one or more of the devices with large leakage current is then determined. Stress-enhancing filler cells are inserted into the optimization zone to replace some or all of the one or more filler cells while placement of the cells in the optimization zone is adjusted based on a leakage reduction analysis.

Abstract: Various aspects of the disclosed technology relate to techniques of determining an across-chip distribution of temperature generated by on-chip devices. Effective thermal conductance and effective thermal capacity for each region of a plurality of regions of a layout design are first extracted. The effective thermal conductance for a region in a metal layer is determined based at least on density information of metal interconnect lines within the region and has components associated with directions of the metal interconnect lines. A thermal circuit is then constructed based on the effective thermal conductance, the effective thermal capacity and heat information of thermal nodes. The heat information of thermal nodes is determined based on an electrical simulation on the integrated circuit associated with the layout design. A thermal simulation is then performed on the thermal circuit to determine temperature information of the thermal nodes.