Abstract: A semiconductor layer stack, a component made therefrom, a component module, and a production method is provided. The semiconductor layer stack has at least two layers (A, B), which, as individual layers, each have an energy position of the Fermi level in the semiconductor band gap, E F - E V < E G 2 applying to the layer (A) and E L - E F < E G 2 applying to the layer (B), with EF the energy position of the Fermi level, EV the energy position of the valence band, EL the energy position of a conduction band and EL?EV the energy difference of the semiconductor band gap EG, the thickness of the layers (A, B) being selected in such a way that a continuous space charge zone region over the layers (A, B) results.

Abstract: The disclosure relates to a method for growing a semiconductor assembly. The method includes the steps of providing a silicon substrate and growing two metal nitride layers, each metal nitride layer being grown by means of a metal target and a plasma. For the second metal nitride layer a higher hydrogen content is used, allowing for better crystal quality than in known methods. The disclosure further relates to a semiconductor assembly that is produced accordingly.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A semiconductor layer stack, a component made therefrom, a component module, and a production method is provided. The semiconductor layer stack has at least two layers (A, B), which, as individual layers, each have an energy position of the Fermi level in the semiconductor band gap, E F - E V < E G 2 applying to the layer (A) and E L - E F < E G 2 applying to the layer (B), with EF the energy position of the Fermi level, EV the energy position of the valence band, EL the energy position of a conduction band and EL?EV the energy difference of the semiconductor band gap EG, the thickness of the layers (A, B) being selected in such a way that a continuous space charge zone region over the layers (A, B) results.

Abstract: A semiconductor layer stack, a component made therefrom, a component module, and a production method is provided. The semiconductor layer stack has at least two layers (A, B), which, as individual layers, each have an energy position of the Fermi level in the semiconductor band gap, E F - E V < E G 2 applying to the layer (A) and E L - E F < E G 2 applying to the layer (B), with EF the energy position of the Fermi level, EV the energy position of the valence band, EL the energy position of a conduction band and EL?EV the energy difference of the semiconductor band gap EG, the thickness of the layers (A, B) being selected in such a way that a continuous space charge zone region over the layers (A, B) results.

Abstract: A micro-electrode array (1) comprising a flexible substrate (2) and a multiplicity of electrodes (3) for electrically measuring neural activity is described. The electrodes (3) are arranged on the substrate (2), project from the plane of the substrate (2) and have a core (4). A plurality of measurement lines (9) that are electrically insulated from one another are arranged around the core (4). Adjacent to the end surface (7) of the core (4), at the end of the electrodes (3) there are a plurality of electrode surfaces (8) arranged in a manner distributed spatially around the end surface (7), said electrode surfaces in each case being electrically conductively connected to an associated measurement line (9). The micro-electrode array (1) is passivated with a polymer-containing material, such as e.g. polyimide, such that only the electrodes (3) electrically contact neural tissue with their electrode surfaces (8, E1, E2).

Abstract: A semiconductor layer stack, a component made therefrom, a component module, and a production method is provided. The semiconductor layer stack has at least two layers (A, B), which, as individual layers, each have an energy position of the Fermi level in the semiconductor band gap, E F - E V < E G 2 applying to the layer (A) and E L - E F < E G 2 applying to the layer (B), with EF the energy position of the Fermi level, EV the energy position of the valence band, EL the energy position of a conduction band and EL?EV the energy difference of the semiconductor band gap EG, the thickness of the layers (A, B) being selected in such a way that a continuous space charge zone region over the layers (A, B) results.

Abstract: The invention relates to, inter alia, a light-emitting semiconductor component comprising the following: —a first mirror (102, 202, 302, 402, 502), —a first conductive layer (103, 203, 303, 403, 503), —a light-emitting layer sequence (104, 204, 304, 404, 504) on a first conductive layer face facing away from the first mirror, and—a second conductive layer (105, 205, 305, 405, 505) on a light-emitting layer sequence face facing away from the first conductive layer, wherein—the first mirror, the first conductive layer, the light-emitting layer sequence, and the second conductive layer are based on a III-nitride compound semiconductor material, —the first mirror is electrically conductive, and—the first mirror is a periodic sequence of homoepitaxial materials with varying refractive indices.

Abstract: A micro-electrode array (1) comprising a flexible substrate (2) and a multiplicity of electrodes (3) for electrically measuring neural activity is described. The electrodes (3) are arranged on the substrate (2), project from the plane of the substrate (2) and have a core (4). A plurality of measurement lines (9) that are electrically insulated from one another are arranged around the core (4). Adjacent to the end surface (7) of the core (4), at the end of the electrodes (3) there are a plurality of electrode surfaces (8) arranged in a manner distributed spatially around the end surface (7), said electrode surfaces in each case being electrically conductively connected to an associated measurement line (9). The micro-electrode array (1) is passivated with a polymer-containing material, such as e.g. polyimide, such that only the electrodes (3) electrically contact neural tissue with their electrode surfaces (8, E1, E2).

Abstract: The invention relates to, inter alia, a light-emitting semiconductor component comprising the following: —a first mirror (102, 202, 302, 402, 502), —a first conductive layer (103, 203, 303, 403, 503), —a light-emitting layer sequence (104, 204, 304, 404, 504) on a first conductive layer face facing away from the first mirror, and —a second conductive layer (105, 205, 305, 405, 505) on a light-emitting layer sequence face facing away from the first conductive layer, wherein —the first mirror, the first conductive layer, the light-emitting layer sequence, and the second conductive layer are based on a III-nitride compound semiconductor material, —the first mirror is electrically conductive, and —the first mirror is a periodic sequence of homoepitaxial materials with varying refractive indices.

Abstract: The invention relates to a component having a transparent conductive nitride layer, characterized by a layer in the AlGaInN system and a doping with a flat donor above a concentration of 5×1019 cm?3.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: The invention relates to a layer system composed of a silicon-based carrier having a single-crystal surface and of a heterostructure applied directly to the single-crystal surface of the carrier. The layer system according to the invention is characterized in that the carrier comprises a silicon substrate doped with one or more dopants, wherein the doped portion extends across at least 30% of the thickness of the doped silicon substrate and a concentration of the dopants in the doped portion of the silicon substrate is predetermined such that a corrected limiting concentration GK meets the condition of formula (1): GK = ? m = i n ? ? N dot i 1 + 5 × 10 22 ? ? cm - 3 N dot i ? ? - E A i / 0.

Abstract: A group-III-nitride based layer sequence fabricated by means of an epitaxial process on a silicon substrate, the layer sequence comprising at least one doped first group-III-nitride layer (105) having a dopant concentration larger than 1×1018 cm?3, a second group-III-nitride layer (106) having a thickness of at least 50 nm and an n-type or p-type dopant concentration of less than 5×1018 cm?3, and an active region made of a group-III-nitride semiconductor material, wherein the first group-III-nitride layer comprises at least one n-type dopant selected from the group of elements formed by germanium, tin, lead, oxygen, sulphur, selenium and tellurium or a at least one p-type dopant, and wherein the active region has a volume density of either screw-type or edge type dislocations below 5×109 mm?3.

Abstract: Semipolar wurtzite Group III nitride-based semiconductor layers and semiconductor components based thereon are described. Group III nitride layers have a broad range of applications in electronics and optoelectronics. Such layers are generally grown on substrates such as sapphire, SiC and, more recently, Si(111). The layers obtained are generally polar or have c-axis orientation in the direction of growth. For many applications in the field of optoelectronics, as well as acoustic applications in SAWs, the growth of non-polar or semipolar Group III nitride layers is interesting or necessary. The process according to the invention permits simple and inexpensive growth of polarisation-reduced Group III nitride layers without prior structuring of the substrate.

Abstract: The invention relates to piezoelectric sensor arrangements, especially sensor arrangements that can be operated in a measuring fluid, in order to be able to detect, for example, elastic properties of the measuring fluid itself or the presence and/or concentration of analyte molecules in the fluid. According to the invention, the sensor arrangement comprises an acoustic resonator which has a sensitive region and is arranged such that a resonance frequency of the sensor arrangement varies according to properties of the measuring fluid. The acoustic resonator is formed by a piezoelectric thin layer resonator and the sensitive region is produced by means of epitaxy, such that transversally polarized vibration modes can be induced.