Abstract: A method of controlling a mobile communications device receiver, which includes: activating the receiver, receiving a voice signal divided into a plurality of voice time intervals, detecting a silent voice time interval from content of the received voice signal, and deactivating the receiver during at least a portion of the silent voice time interval. In addition, the method may also include: receiving a signaling signal divided into a plurality of signaling time intervals, detecting an empty signaling time interval from the plurality of signaling time intervals, and deactivating the receiver during at least a portion of the empty signaling time interval.

Abstract: A method of controlling a mobile communications device receiver, which includes: activating the receiver, receiving a voice signal divided into a plurality of voice time intervals, detecting a silent voice time interval from content of the received voice signal, and deactivating the receiver during at least a portion of the silent voice time interval. In addition, the method may also include: receiving a signaling signal divided into a plurality of signaling time intervals, detecting an empty signaling time interval from the plurality of signaling time intervals, and deactivating the receiver during at least a portion of the empty signaling time interval.

Abstract: A circuit according to an example includes a receiver circuit configured to receive a signal including a data stream, the data stream including at least one block of data, a block of the at least one block of data including at least two sub-blocks, a payload of the block being redundantly encoded in the at least two sub-blocks, and the at least two sub-blocks of the block being consistently arranged over time inside the block. The circuit further includes a control circuit configured to switch the receiver circuit into a non-ready-to-receive state during at least a part of at least one of the at least two sub-blocks of the block, when an enable condition is fulfilled.

Abstract: A circuit according to an example includes a receiver circuit configured to receive a signal including a data stream, the data stream including at least one block of data, a block of the at least one block of data including at least two sub-blocks, a payload of the block being redundantly encoded in the at least two sub-blocks, and the at least two sub-blocks of the block being consistently arranged over time inside the block. The circuit further includes a control circuit configured to switch the receiver circuit into a non-ready-to-receive state during at least a part of at least one of the at least two sub-blocks of the block, when an enable condition is fulfilled.

Abstract: A method of detecting a control channel includes receiving data transmitted via a control channel. A path metric and a correction term is computed based on the received data. A decision metric representing a sum or a difference of the path metric and the correction term is computed. Based on the decision metric, it is decided on a detection of the control channel.

Abstract: A method of detecting a control channel includes receiving data transmitted via a control channel. A path metric and a correction term is computed based on the received data. A decision metric representing a sum or a difference of the path metric and the correction term is computed. Based on the decision metric, it is decided on a detection of the control channel.

Abstract: Depending on the sequence of the decoded payload signal bits (am1, . . . , amA) and redundancy checking bits (pm1, . . . , pmL) which are produced by the Viterbi traceback, either some of these bits are inserted by means of a distribution device (1) from the front into a linear feedback shift register (10), or some of these bits are inserted by means of the distribution device (1) from the rear into a linear feedback shift register (10), or all of them are inserted into a linear feedback shift register (20) from the rear with the allocated coefficients being unchanged, or all of them are inserted into a shift register from the front with the allocated coefficients being inverted. This allows a redundancy checking process to be carried out on a transmitted data block in the shift register (10; 20) without temporary storage of the bits produced by the decoding process.